ultraembedded/cores ultraembedded/cores

  • Stars
    star
    598
  • Rank 74,853 (Top 2 %)
  • Language Verilog
  • Created over 9 years ago
  • Updated over 3 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
ultraembedded/cores
github

ultraembedded

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Various HDL (Verilog) IP Cores

Various HDL (Verilog) IP Cores

Github: http://github.com/ultraembedded/cores

Cloning

This repo contains submodules, to clone them;

git clone --recursive https://github.com/ultraembedded/cores.git

Catalogue

Name Description
asram16_axi4 AXI4 -> Async SRAM (16-bit) Interface
dbg_bridge UART -> AXI4 Debug Bridge
dvi_framebuffer DVI/HDMI framebuffer with AXI-4 bus master
ftdi_async_bridge FTDI Asynchronous FIFO Interface (Wishbone)
ftdi_bridge FTDI Asynchronous/Synchronous FIFO Interface (AXI-4)
ft60x_axi FTDI FT601 USB3.0 to high-performance AXI4 bus master
i2s I2S Master
irq_ctrl Simple Linux support interrupt controller
sdram Simple SDRAM Controller (Wishbone)
sdram_axi4 Simple SDRAM Controller (AXI-4)
spdif SPDIF Transmitter
spiflash SPI-Flash XIP Interface
spilite_axi4l SPI-Lite SPI Master Interface
uart UART
ulpi_wrapper ULPI Link Wrapper
usb_bridge USB -> AXI4-Lite Debug Bridge
usb_cdc USB CDC Device
usb_device USB Peripheral Interface
usb_fs_phy USB Full Speed PHY
usb_host USB 1.1 Host Controller
usb_sniffer USB Sniffer
usb_serial USB to UART

More Repositories

1

riscv

RISC-V CPU Core (RV32IM)
Verilog
984
star
2

biriscv

32-bit Superscalar RISC-V CPU
Verilog
701
star
3

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs
Verilog
260
star
4

FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
C
237
star
5

core_jpeg

High throughput JPEG decoder in Verilog for FPGA
Verilog
166
star
6

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
Verilog
87
star
7

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs
C
77
star
8

riscv_soc

Basic RISC-V Test SoC
Verilog
76
star
9

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m
C++
74
star
10

core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master
C++
73
star
11

libhelix-mp3

Fixed-point MP3 decoder (RISC-V port)
C
66
star
12

core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer
Verilog
65
star
13

core_audio

Audio controller (I2S, SPDIF, DAC)
Verilog
64
star
14

core_usb_cdc

Basic USB-CDC device core (Verilog)
Verilog
61
star
15

core_sdram_axi4

SDRAM controller with AXI4 interface
C++
59
star
16

usb_sniffer

High Speed USB 2.0 capture device based on miniSpartan6+
C
56
star
17

core_soc

Basic Peripheral SoC (SPI, GPIO, Timer, UART)
Verilog
51
star
18

core_uriscv

Another tiny RISC-V implementation
Verilog
49
star
19

fat_io_lib

Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.
C
48
star
20

usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
Verilog
42
star
21

core_dbg_bridge

UART -> AXI Bridge
Verilog
41
star
22

riscv-linux-boot

Trivial RISC-V Linux binary bootloader
C
38
star
23

core_usb_fs_phy

USB Full Speed PHY
Verilog
35
star
24

core_spiflash

SPI-Flash XIP Interface (Verilog)
Verilog
33
star
25

core_usb_bridge

USB -> AXI Debug Bridge
Verilog
32
star
26

core_usb_uart

USB serial device (CDC-ACM)
Verilog
27
star
27

core_jpeg_decoder

HW JPEG decoder wrapper with AXI-4 DMA
Verilog
24
star
28

core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)
Verilog
24
star
29

riscv_sbc

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Verilog
24
star
30

fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
C
22
star
31

core_enet

Ethernet MAC 10/100 Mbps
Verilog
21
star
32

core_mmc

MMC (and derivative standards) host controller
Verilog
21
star
33

minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player
Verilog
21
star
34

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
Verilog
20
star
35

core_ulpi_wrapper

ULPI Link Wrapper (USB Phy Interface)
C++
19
star
36

core_usb_sniffer

USB capture IP
Verilog
18
star
37

riscv32_linux_from_scratch

RISC-V 32-bit Linux From Scratch
Makefile
18
star
38

librtos

Very basic real time operating system for embedded systems...
C
14
star
39

ecpix-5

Projects for the ECPiX-5 - a ECP5 FPGA board.
Verilog
12
star
40

minispartan6

Projects for the Scarab Minispartan6+ FPGA board
VHDL
12
star
41

core_ram_tester

AXI-4 RAM Tester Component
Verilog
11
star
42

altor32

AltOr32 - Alternative Lightweight OpenRisc CPU
Verilog
11
star
43

armv6m-sim

Simple instruction set simulator for ARMv6-M (Cortex M0)
C++
10
star
44

core_mpx

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA
Verilog
9
star
45

xc6_bus_pirate

XC6 Bus Pirate (FPGA based multi-tool)
Verilog
7
star
46

orangecrab

Test projects for the OrangeCrab ECP5 FPGA board
Verilog
6
star
47

ecpix5-test

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board
Verilog
6
star
48

riscv-sw-test

C++
5
star
49

riscv-linux-prebuilt

RISC-V Linux prebuilt images
5
star
50

embedded_httpd

Embedded HTTP Server
C
3
star
51

rp2040_blinky

Simple blinky example for the RP2040 that does not require cmake
C++
3
star