Discover ucb-bar/sha3-workload Open Source project

Berkeley's Spatial Array Generator

1,415

gemmini

chisel tutorial exercises and answers

668

chisel-tutorial

educational microarchitectures for risc-v isa

643

riscv-sodor

Simple RISC-V 3-stage Pipeline in Chisel

641

riscv-mini

chisel2-deprecated

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

berkeley-softfloat-3

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

The batteries-included testing and formal verification library for Chisel-based RTL designs.

206

chiseltest

riscv-torture

constellation

A Chisel RTL generator for network-on-chip interconnects

Microarchitecture implementation of the decoupled vector-fetch accelerator

143

hwacha

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

139

esp-llvm

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

123

midas

testchipip

Fork of upstream onnxruntime focused on supporting risc-v accelerators

sha3

Verilog

onnxruntime-riscv

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

cosa

Memory System Microbenchmarks

ccbench

zscale

Z-scale Microarchitectural Implementation of RV32 ISA

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

chisel-gui

A prototype GUI for chisel-development

Template for projects using the Hwacha data-parallel accelerator

berkeley-testfloat-3

TestFloat release 3

hwacha-template

barstools

Useful utilities for BAR projects

A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.

RoSE

autophase

Wrapper for ETH Ariane Core

cva6-wrapper

Wraps the NVDLA project for Chipyard integration

riscv-benchmarks

nvdla-wrapper

Verilog

MoCA

Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V

riscv-blas

Fortran

libgloss-htif

A libgloss replacement for RISC-V that supports HTIF

esp-isa-sim

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

asyncqueue

Lightweight re-packaging of AsyncQueue library from rocket-chip

Support for zScale on Spartan6 FPGAs

fpga-spartan6

Verilog

shuttle

A Rocket-based RISC-V superscalar in-order core

chisel-awl

protoacc

midas-examples

Simple MIDAS Examples

A template for developing custom FIRRTL transforms

firrtl-transform-tutorial

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design

vaesa

esp-tools

Hammer plugins for Cadence tools

hammer-cadence-plugins

prebuilt images for zedboard zynq fpga

fpga-images-zedboard

context-dependent-environments

A Scala library for Context-Dependent Evironments

firrtl-uclid

chisel-sift

Hammer plugins for synopsys tools

hammer-synopsys-plugins

Tools for integrating DspTools components into a rocket-chip

rocket-dsp-utils

midas-release

MIDAS Public Release

MIDAS RocketChip Template

midas-top-release

Curated set of DockerFiles for RISC-V projects

riscv-docker-images

Dockerfile

FFTGenerator

plsi-mdf

Macro description format

FireMarshal workload for SPEC2017

spec2017-workload

A zynq host-platform shell for midas generated simulators.

midas-zynq

Tcl

maltese-smt

Archived! All relevant features are now part of the firrtl smt backend or the chiseltest library.

Base NVDLA Workload for FireMarshal

nvdla-workload

DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators

hwacha-net

dosa

compress-acc

Chisel Fixed-Point Arithmetic Library

fixedpoint

Custom extensions to the RISC-V tests for the UCB-BAR ESP project

esp-tests

chipyard-toolchain-prebuilt

Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.

Makefile

pwm-chisel-example

pwm-chisel-example for risc-v summer 2016 workshop

cs152-lab4

CS152 Lab 4

riscv-tools-feedstock

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

stac-top

OpenCL kernels for ucb-bar hardware

opencl-kernels

bits

chipper-tutorial

coremark-workload

FireMarshal workload for CoreMark EEMBC

Collection of device models for spike

spike-devices

2023-winter-demo-project-power-aka-bora

rerocc

Converts a VCD file to a Chisel tester input file

vcd2step

UC Berkeley Copy of the FIRRTL Compiler

pocl

firrtl2

A tool that generates Chisel torture tests

chisel-torture

fpga-images-zybo

ibex-wrapper

Wrapper for lowRISC Ibex

Berkeley Architecture Research pre-Fetchers

bar-fetchers

LBNL TORCH Reference Kernels

lbnl-torch

chisel-library-template

Use for developing Chisel+Firrtl libraries

Baremetal-IDE

A submodule of Chipyard https://github.com/ucb-bar/chipyard

HTML

fpga-images-zc706

caliptra-aes-acc

SystemVerilog

testers-regression

Uses gcd to do some really basic speed comparisons

Custom extensions to the RISC-V test environments for the UCB-BAR ESP project

esp-test-env

chisel-release

Chisel release tooling

esp-tools-feedstock