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chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and moregemmini
Berkeley's Spatial Array Generatorchisel-tutorial
chisel tutorial exercises and answersriscv-sodor
educational microarchitectures for risc-v isariscv-mini
Simple RISC-V 3-stage Pipeline in Chiselchisel2-deprecated
fpga-zynq
Support for Rocket Chip on Zynq FPGAsberkeley-hardfloat
hammer
Hammer: Highly Agile Masks Made Effortlessly from RTLberkeley-softfloat-3
SoftFloat release 3dsptools
A Library of Chisel3 Tools for Digital Signal Processingchiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.riscv-torture
RISC-V Torture Testconstellation
A Chisel RTL generator for network-on-chip interconnectshwacha
Microarchitecture implementation of the decoupled vector-fetch acceleratoresp-llvm
UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVMmidas
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTLtestchipip
sha3
onnxruntime-riscv
Fork of upstream onnxruntime focused on supporting risc-v acceleratorscosa
A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)ccbench
Memory System Microbenchmarkszscale
Z-scale Microarchitectural Implementation of RV32 ISAgemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul acceleratorchisel-gui
A prototype GUI for chisel-developmentberkeley-testfloat-3
TestFloat release 3hwacha-template
Template for projects using the Hwacha data-parallel acceleratorbarstools
Useful utilities for BAR projectsRoSE
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.autophase
cva6-wrapper
Wrapper for ETH Ariane Coreriscv-benchmarks
riscv-blas
Custom BLAS and LAPACK Cross-Compilation Framework for RISC-Vnvdla-wrapper
Wraps the NVDLA project for Chipyard integrationMoCA
libgloss-htif
A libgloss replacement for RISC-V that supports HTIFesp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP projectasyncqueue
Lightweight re-packaging of AsyncQueue library from rocket-chipfpga-spartan6
Support for zScale on Spartan6 FPGAsshuttle
A Rocket-based RISC-V superscalar in-order corechisel-awl
protoacc
midas-examples
Simple MIDAS Examplesfirrtl-transform-tutorial
A template for developing custom FIRRTL transformsvaesa
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Designesp-tools
hammer-cadence-plugins
Hammer plugins for Cadence toolsfpga-images-zedboard
prebuilt images for zedboard zynq fpgacontext-dependent-environments
A Scala library for Context-Dependent Evironmentsfirrtl-uclid
chisel-sift
hammer-synopsys-plugins
Hammer plugins for synopsys toolsrocket-dsp-utils
Tools for integrating DspTools components into a rocket-chipmidas-release
MIDAS Public Releasemidas-top-release
MIDAS RocketChip Templateriscv-docker-images
Curated set of DockerFiles for RISC-V projectsFFTGenerator
plsi-mdf
Macro description formatspec2017-workload
FireMarshal workload for SPEC2017midas-zynq
A zynq host-platform shell for midas generated simulators.maltese-smt
Archived! All relevant features are now part of the firrtl smt backend or the chiseltest library.nvdla-workload
Base NVDLA Workload for FireMarshalhwacha-net
dosa
DOSA: Differentiable Model-Based One-Loop Search for DNN Acceleratorscompress-acc
fixedpoint
Chisel Fixed-Point Arithmetic Libraryesp-tests
Custom extensions to the RISC-V tests for the UCB-BAR ESP projectpwm-chisel-example
pwm-chisel-example for risc-v summer 2016 workshopcs152-lab4
CS152 Lab 4riscv-tools-feedstock
stac-top
The SRAM timing analysis chip for verifying SRAMs generated by SRAM22opencl-kernels
OpenCL kernels for ucb-bar hardwarebits
Firebox Benchmarkschipper-tutorial
tutorial for chippercoremark-workload
FireMarshal workload for CoreMark EEMBCspike-devices
Collection of device models for spike2023-winter-demo-project-power-aka-bora
rerocc
vcd2step
Converts a VCD file to a Chisel tester input filepocl
firrtl2
UC Berkeley Copy of the FIRRTL Compilerchisel-torture
A tool that generates Chisel torture testsfpga-images-zybo
ibex-wrapper
Wrapper for lowRISC Ibexbar-fetchers
Berkeley Architecture Research pre-Fetcherslbnl-torch
LBNL TORCH Reference Kernelschisel-library-template
Use for developing Chisel+Firrtl librariesBaremetal-IDE
A submodule of Chipyard https://github.com/ucb-bar/chipyardfpga-images-zc706
caliptra-aes-acc
testers-regression
Uses gcd to do some really basic speed comparisonsesp-test-env
Custom extensions to the RISC-V test environments for the UCB-BAR ESP projectchisel-release
Chisel release toolingsha3-workload
FireMarshal workload for the sha3 example rocc acceleratoresp-tools-feedstock
stac-bringup
Bringup infrastructure for the SRAM Timing Analysis Chipesp-opcodes
Custom extensions to the RISC-V opcodes for the UCB-BAR ESP projectesp-gnu-toolchain
Custom extensions to the RISC-V toolchain for the UCB-BAR ESP projectBaremetal-llama
tsi
Standalone tethered serial interface (TSI) implementation with CLI utilities.Love Open Source and this site? Check out how you can help us