ucb-bar/hwacha

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146
Rank 252,769 (Top 5 %)
Language
Scala
Created almost 13 years ago
Updated 10 months ago

ucb-bar/hwacha

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Microarchitecture implementation of the decoupled vector-fetch accelerator

Hwacha Vector-Thread Co-Processor Sources

To use this co-processor, include this repo as a git submodule and add it as to your chip's build.sbt as a Project, e.g.

lazy val hwacha = Project(file("hwacha"), "hwacha")
  .settings(buildSettings)
  .dependsOn(rocketchip)

Hwacha depends on the Rocket Chip project. Make sure the proper JARs are installed. For more information on how to use this co-processor, refer to (https://github.com/ucb-bar/chipyard).

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

gemmini

Berkeley's Spatial Array Generator

riscv-sodor

educational microarchitectures for risc-v isa

chisel-tutorial

chisel tutorial exercises and answers

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel2-deprecated

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

berkeley-softfloat-3

SoftFloat release 3

constellation

A Chisel RTL generator for network-on-chip interconnects

riscv-torture

RISC-V Torture Test

esp-llvm

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

midas

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

testchipip

onnxruntime-riscv

Fork of upstream onnxruntime focused on supporting risc-v accelerators

sha3

cosa

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

ccbench

Memory System Microbenchmarks

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

zscale

Z-scale Microarchitectural Implementation of RV32 ISA

chisel-gui

A prototype GUI for chisel-development

berkeley-testfloat-3

TestFloat release 3

hwacha-template

Template for projects using the Hwacha data-parallel accelerator

RoSE

A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.

barstools

Useful utilities for BAR projects

autophase

shuttle

A Rocket-based RISC-V superscalar in-order core

riscv-benchmarks

MoCA

saturn-vectors

Chisel RISC-V Vector 1.0 Implementation

libgloss-htif

A libgloss replacement for RISC-V that supports HTIF

nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

cva6-wrapper

Wrapper for ETH Ariane Core

esp-isa-sim

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

asyncqueue

Lightweight re-packaging of AsyncQueue library from rocket-chip

riscv-blas

Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V

fpga-spartan6

Support for zScale on Spartan6 FPGAs

chisel-awl

dosa

DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators

Baremetal-NN

A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on RISC-V research chips.

rocket-dsp-utils

Tools for integrating DspTools components into a rocket-chip

protoacc

midas-examples

Simple MIDAS Examples

vaesa

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design

firrtl-transform-tutorial

A template for developing custom FIRRTL transforms

hammer-cadence-plugins

Hammer plugins for Cadence tools

FFTGenerator

esp-tools

fpga-images-zedboard

prebuilt images for zedboard zynq fpga

compress-acc

context-dependent-environments

A Scala library for Context-Dependent Evironments

firrtl-uclid

plsi-mdf

Macro description format

chisel-sift

hammer-synopsys-plugins

Hammer plugins for synopsys tools

midas-release

MIDAS Public Release

fixedpoint

Chisel Fixed-Point Arithmetic Library

midas-top-release

MIDAS RocketChip Template

riscv-docker-images

Curated set of DockerFiles for RISC-V projects

spec2017-workload

FireMarshal workload for SPEC2017

midas-zynq

A zynq host-platform shell for midas generated simulators.

spike-devices

Collection of device models for spike

rerocc

Baremetal-IDE

A submodule of Chipyard https://github.com/ucb-bar/chipyard

maltese-smt

Archived! All relevant features are now part of the firrtl smt backend or the chiseltest library.

esp-tests

Custom extensions to the RISC-V tests for the UCB-BAR ESP project

nvdla-workload

Base NVDLA Workload for FireMarshal

hwacha-net

firrtl2

UC Berkeley Copy of the FIRRTL Compiler

AuRORA

Virtualized Accelerator Orchestration for Multi-Tenant Workloads

pyuartsi

A standalone implementation of the Tethered Serial Interface (TSI) in Python.

chipyard-toolchain-prebuilt

Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.

pwm-chisel-example

pwm-chisel-example for risc-v summer 2016 workshop

cs152-lab4

ibex-wrapper

Wrapper for lowRISC Ibex

riscv-tools-feedstock

stac-top

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

opencl-kernels

OpenCL kernels for ucb-bar hardware

chipper-tutorial

tutorial for chipper

coremark-workload

FireMarshal workload for CoreMark EEMBC

bits

Firebox Benchmarks

2023-winter-demo-project-power-aka-bora

Baremetal-llama

chipyard-cs152-sp24

riscv-coremark-pro

Compiles coremark-pro for riscv64 baremetal

vcd2step

Converts a VCD file to a Chisel tester input file

pocl

chisel-release

Chisel release tooling

chisel-torture

A tool that generates Chisel torture tests

fpga-images-zybo

ara-wrapper

bar-fetchers

Berkeley Architecture Research pre-Fetchers

lbnl-torch

LBNL TORCH Reference Kernels

chisel-library-template

Use for developing Chisel+Firrtl libraries

fpga-images-zc706

baseband-modem

Digital baseband-modem processor for 2.4 GHz Bluetooth Low Energy and IEEE 802.15.4 standards

Jupyter Notebook

caliptra-aes-acc