Discover ucb-bar/dosa Open Source project

Berkeley's Spatial Array Generator

1,601

gemmini

educational microarchitectures for risc-v isa

793

riscv-sodor

chisel tutorial exercises and answers

673

chisel-tutorial

Simple RISC-V 3-stage Pipeline in Chisel

643

riscv-mini

chisel2-deprecated

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

The batteries-included testing and formal verification library for Chisel-based RTL designs.

253

chiseltest

A Library of Chisel3 Tools for Digital Signal Processing

220

dsptools

berkeley-softfloat-3

constellation

A Chisel RTL generator for network-on-chip interconnects

riscv-torture

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

146

esp-llvm

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

123

midas

testchipip

Fork of upstream onnxruntime focused on supporting risc-v accelerators

onnxruntime-riscv

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

sha3

Verilog

cosa

Memory System Microbenchmarks

ccbench

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

zscale

Z-scale Microarchitectural Implementation of RV32 ISA

chisel-gui

A prototype GUI for chisel-development

Template for projects using the Hwacha data-parallel accelerator

berkeley-testfloat-3

TestFloat release 3

hwacha-template

RoSE

A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.

Useful utilities for BAR projects

barstools

autophase

A Rocket-based RISC-V superscalar in-order core

shuttle

riscv-benchmarks

MoCA

Chisel RISC-V Vector 1.0 Implementation

saturn-vectors

Assembly

libgloss-htif

A libgloss replacement for RISC-V that supports HTIF

nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

Verilog

cva6-wrapper

Wrapper for ETH Ariane Core

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

esp-isa-sim

asyncqueue

Lightweight re-packaging of AsyncQueue library from rocket-chip

Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V

riscv-blas

Fortran

fpga-spartan6

Support for zScale on Spartan6 FPGAs

Verilog

chisel-awl

A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on RISC-V research chips.

Baremetal-NN

rocket-dsp-utils

Tools for integrating DspTools components into a rocket-chip

protoacc

midas-examples

Simple MIDAS Examples

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design

vaesa

A template for developing custom FIRRTL transforms

firrtl-transform-tutorial

Hammer plugins for Cadence tools

hammer-cadence-plugins

FFTGenerator

esp-tools

prebuilt images for zedboard zynq fpga

fpga-images-zedboard

compress-acc

A Scala library for Context-Dependent Evironments

context-dependent-environments

firrtl-uclid

plsi-mdf

Macro description format

chisel-sift

Hammer plugins for synopsys tools

hammer-synopsys-plugins

midas-release

MIDAS Public Release

Chisel Fixed-Point Arithmetic Library

fixedpoint

MIDAS RocketChip Template

midas-top-release

Curated set of DockerFiles for RISC-V projects

riscv-docker-images

Dockerfile

spec2017-workload

FireMarshal workload for SPEC2017

A zynq host-platform shell for midas generated simulators.

midas-zynq

Tcl

spike-devices

Collection of device models for spike

rerocc

A submodule of Chipyard https://github.com/ucb-bar/chipyard

Baremetal-IDE

HTML

maltese-smt

Archived! All relevant features are now part of the firrtl smt backend or the chiseltest library.

Custom extensions to the RISC-V tests for the UCB-BAR ESP project

esp-tests

nvdla-workload

Base NVDLA Workload for FireMarshal

UC Berkeley Copy of the FIRRTL Compiler

hwacha-net

firrtl2

Virtualized Accelerator Orchestration for Multi-Tenant Workloads

AuRORA

pyuartsi

A standalone implementation of the Tethered Serial Interface (TSI) in Python.

Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.

chipyard-toolchain-prebuilt

Makefile

pwm-chisel-example

pwm-chisel-example for risc-v summer 2016 workshop

cs152-lab4

CS152 Lab 4

ibex-wrapper

Wrapper for lowRISC Ibex

riscv-tools-feedstock

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

stac-top

OpenCL kernels for ucb-bar hardware

opencl-kernels

chipper-tutorial

tutorial for chipper

FireMarshal workload for CoreMark EEMBC

coremark-workload

bits

Firebox Benchmarks

2023-winter-demo-project-power-aka-bora

Compiles coremark-pro for riscv64 baremetal

Baremetal-llama

chipyard-cs152-sp24

riscv-coremark-pro

Makefile

vcd2step

Converts a VCD file to a Chisel tester input file

A tool that generates Chisel torture tests

pocl

chisel-release

Chisel release tooling

chisel-torture

fpga-images-zybo

ara-wrapper

Berkeley Architecture Research pre-Fetchers

bar-fetchers