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serv
SERV - The SErial RISC-V CPUfusesoc
Package manager and build abstraction tool for FPGA/ASIC developmentedalize
An abstraction library for interfacing EDA toolscorescore
CoreScoreipyxact
Python-based IP-XACT parserfifo
Generic FIFO implementation with optional FWFTobserver
wb_intercon
Wishbone interconnect utilitiessubservient
Small SERV-based SoC primarily for OpenMPW tapeoutfusesocotb
Quick'n'dirty FuseSoC+cocotb exampleverilatio
A protocol for communicating with HDL simulations over websocketscryptech-cores
Core description files for the Cryptech projectde0_nano
wb_bfm
Wishbone Bus Functional Modelanother_serv
SERV running Another World under Verilatoror1k-ipxact
IP-Xact files for OpenRISC-based systemsipxact_gen
ca_workshop_munich
Material for the CHIPS Alliance workshop in Munichfusesoc_vunit_demo
Demo project for FuseSoC + VUnit integrationreset_test
Reset demo for blog postwb_streamer
Wishbone component for converting data streams to wishbone transactionspdklite
de0_nano_ipxact
stream_utils
Utility functions for data streamslibaxis
Library of RTL components for AXI Stream infrastructureor1k_bootloaders
OpenRISC 1000-compatible bootloadersLove Open Source and this site? Check out how you can help us