Olof Kindgren (@olofk)
  • Stars
    star
    2,951
  • Global Rank 10,036 (Top 0.4 %)
  • Followers 665
  • Following 1
  • Registered over 12 years ago
  • Most used languages
    Verilog
    56.0 %
    Python
    20.0 %
    C
    8.0 %
    VHDL
    8.0 %
    Assembly
    4.0 %
    Tcl
    4.0 %

Top repositories

1

serv

SERV - The SErial RISC-V CPU
Verilog
1,229
star
2

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development
Python
1,151
star
3

edalize

An abstraction library for interfacing EDA tools
Python
613
star
4

corescore

CoreScore
Verilog
109
star
5

ipyxact

Python-based IP-XACT parser
Python
108
star
6

vidbo

Virtual Development Board
C
52
star
7

fifo

Generic FIFO implementation with optional FWFT
Verilog
42
star
8

observer

Verilog
37
star
9

wb_intercon

Wishbone interconnect utilities
Verilog
28
star
10

subservient

Small SERV-based SoC primarily for OpenMPW tapeout
Verilog
25
star
11

fusesocotb

Quick'n'dirty FuseSoC+cocotb example
Python
15
star
12

verilatio

A protocol for communicating with HDL simulations over websockets
10
star
13

cryptech-cores

Core description files for the Cryptech project
Tcl
6
star
14

de0_nano

Verilog
6
star
15

wb_bfm

Wishbone Bus Functional Model
Verilog
5
star
16

another_serv

SERV running Another World under Verilator
C
3
star
17

or1k-ipxact

IP-Xact files for OpenRISC-based systems
3
star
18

ipxact_gen

Python
3
star
19

ca_workshop_munich

Material for the CHIPS Alliance workshop in Munich
Verilog
2
star
20

fusesoc_vunit_demo

Demo project for FuseSoC + VUnit integration
VHDL
2
star
21

reset_test

Reset demo for blog post
Verilog
2
star
22

wb_streamer

Wishbone component for converting data streams to wishbone transactions
Verilog
2
star
23

pdklite

Verilog
2
star
24

de0_nano_ipxact

Verilog
2
star
25

stream_utils

Utility functions for data streams
Verilog
1
star
26

libaxis

Library of RTL components for AXI Stream infrastructure
VHDL
1
star
27

or1k_bootloaders

OpenRISC 1000-compatible bootloaders
Assembly
1
star