estija/Verilog-assignments estija/Verilog-assignments

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  • Language Verilog
  • Created over 7 years ago
  • Updated about 7 years ago
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estija/Verilog-assignments
github

estija

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Repository Details

This repository contains some Verilog files in which DLD concepts like adders, multiplexer, multiplier, flip-flops, encoder etc. have been implemented.

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