aminrashidbeigi/16bit_adder

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Created over 7 years ago
Updated about 5 years ago

aminrashidbeigi/16bit_adder

aminrashidbeigi

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Implementation of 16 bits carry look ahead and ripple carry adders

SAYEH

SAYEH cpu-memory basic computer

BS-thesis

Design and implementation goods information system of stores and warehouses

SAYEH-Compiler

SAYEH-Cache

implementing SAYEH cache using VHDL

CADSD-homeworks

Solutions of Computer Aided Digital System Design (FPGA) Course Homeworks

gaussians-streaming-data

Implementation of "Learning Mixture of Gaussians with Streaming Data" paper

stackoverflow

simple stackoverflow website by laravel

mrf-segmentation-denoising

Probabilistic Graphical Models final project

Jupyter Notebook

vuejs-learning

ai-classical-search-algorithms

ai-local-search-algorithms

smart-house

Computer Aided Digital System Design (FPGA) Course Final project

laravel-blog

one-time-data

Data that you may need once in your lifetime!

signal-and-systems-project

Final project of Signal and Systems Course

vivado-zero-to-hundred

video Tool Command Language (TCL) from creating a project to generate its bitstream

dare-house

BS thesis: intelligent warehouse management system

http-dns-proxy

traffic-light-logic

Implementation of traffic light logic as Logic Design course final project

CountingSort

Multi thread and multi process implementation of Counting sort for Operating Systems course

railway-database

Principles of Database Design final project

dice-game

Project of Internet Engineering course by PHP (Laravel) and Vue js (Nuxt js)