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signalflip-js
verilator testbench w/ Javascript using N-APIelastic-buffer
buffers for valid-ready designsreciprocal-sv
Fixed point reciprocal in SystemVerilogleading-zeroes-counter
Leading zeroes counter (SystemVerilog)eth-uvm
de0-nano-projects
de0 nano projectsbasic-signalflip-example
Signalflip example: simulate counter rtlmpw3-nco
NCO on mpw3 (group submission)spinal-interfaces
interfaces such as jtag, apb, and others in SpinalHDLusb_uart_tinybx
working usb uart on tinyfpga bxtun2udp
tun to udp python scriptulcdAccel-demo
4DGL-uLCD-SE with accelerometer project on LPC1768. Ball moves with accelerometer vector.ldpc_ccsds
LDPC CCSDS octavesva_examples
symbiyosys sva exapleslfsrLED-board
555 timer and shift register chip use to create led light up patternInternetClock
Clock display using 4DGL-uLCD-SE, Ethernet, and LPC1768 (mbed)two-input-arbiter
Two input arbiterDSP-C
DSP functions in C++/Cfixed2float
Convert fixed point to float and vice-versaAPB3-config-regs
Implements two config registers with APB3 interface. Verification testbench done in verilator using signalflip-jsriscv-sv
RISC-V implementationfp_reciprocal
Fixed point implementation of reciprocal (described in JS but can be easily ported to verilog)vpiexamples
vpi (verilog pli) exmaplesLove Open Source and this site? Check out how you can help us