ameetgohil/reciprocal-sv

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Rank 3,304,323 (Top 66 %)
Language Makefile
License
MIT License
Created over 4 years ago
Updated over 3 years ago

ameetgohil/reciprocal-sv

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Fixed point reciprocal in SystemVerilog

signalflip-js

verilator testbench w/ Javascript using N-API

elastic-buffer

buffers for valid-ready designs

leading-zeroes-counter

Leading zeroes counter (SystemVerilog)

eth-uvm

de0-nano-projects

de0 nano projects

basic-signalflip-example

Signalflip example: simulate counter rtl

mpw3-nco

NCO on mpw3 (group submission)

spinal-interfaces

interfaces such as jtag, apb, and others in SpinalHDL

usb_uart_tinybx

working usb uart on tinyfpga bx

tun2udp

tun to udp python script

ulcdAccel-demo

4DGL-uLCD-SE with accelerometer project on LPC1768. Ball moves with accelerometer vector.

ldpc_ccsds

LDPC CCSDS octave

sva_examples

symbiyosys sva exaples

lfsrLED-board

555 timer and shift register chip use to create led light up pattern

InternetClock

Clock display using 4DGL-uLCD-SE, Ethernet, and LPC1768 (mbed)

two-input-arbiter

Two input arbiter

DSP-C

DSP functions in C++/C

fixed2float

Convert fixed point to float and vice-versa

APB3-config-regs

Implements two config registers with APB3 interface. Verification testbench done in verilator using signalflip-js

riscv-sv

RISC-V implementation

fp_reciprocal

Fixed point implementation of reciprocal (described in JS but can be easily ported to verilog)

vpiexamples

vpi (verilog pli) exmaples

DSP-STM32

DSP projects on STM32F429ZI Nucleo board