ZiyangYE/LicheeTang20K_DDR_Test ZiyangYE/LicheeTang20K_DDR_Test

  • Stars
    star
    16
  • Rank 1,304,049 (Top 26 %)
  • Language Verilog
  • License
    BSD 3-Clause "New...
  • Created over 2 years ago
  • Updated over 1 year ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
ZiyangYE/LicheeTang20K_DDR_Test
github

ZiyangYE

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

The DDR Test Firmware for LicheeTang20K.

More Repositories

1

General-Slow-DDR3-Interface

A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
Verilog
34
star
2

DeepFakeVoice

from CorentinJ / Real-Time-Voice-Cloning
Python
23
star
3

crash_analysis

Analysis for the May 7th, 2021, Shaoguan Guangdong crash.
Python
15
star
4

Verilog_TCP

Highly specialized TCP module. Simple and high-performance. No ARP support.
SystemVerilog
7
star
5

Downloader

Downloader by CY68013
5
star
6

verilog_UDP

SystemVerilog
5
star
7

Route_Planning

MATLAB
3
star
8

LicheeTang25k_SDRAM

SDRAM controller for LicheeTang25k
SystemVerilog
3
star
9

Super-Scalar-RV32

Learn to design super scalar processors and use advanced HDLs. Design from scratch.
Verilog
2
star
10

locker

This is a py program which may detect the USB device and do sth.(lock, etc.)
Python
2
star
11

USB_Clock_Generator

A Clock Generator with USB Type-C, based on CH551 and MS5351 (Compatible with Si5351)
C
2
star
12

Mobile-Heartrate-Monitor

mobile heartrate monitor on AT32F403A with RT-Thread
C
2
star
13

HDW_6807

Drive HDW_6807 (KS0108) with STM32F103
C
1
star
14

LicheeTang25k_VexRV_micro

Verilog
1
star