YE ZIYANG (@ZiyangYE)
github

ZiyangYE

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  • Stars
    star
    125
  • Global Rank 175,569 (Top 7 %)
  • Followers 32
  • Following 10
  • Registered about 6 years ago
  • Most used languages
    Verilog     28.6 %
    C
         21.4 %
    SystemVerilog     21.4 %
    Python
         21.4 %
    MATLAB
         7.1 %
  • Location πŸ‡―πŸ‡΅ Japan
  • Country Total Rank 4,955
  • Country Ranking
    SystemVerilog     8
    Verilog     9
    MATLAB
         143
    Python
         1,080
    C
         1,410

Top repositories

1

General-Slow-DDR3-Interface

A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
Verilog
34
star
2

DeepFakeVoice

from CorentinJ / Real-Time-Voice-Cloning
Python
23
star
3

LicheeTang20K_DDR_Test

The DDR Test Firmware for LicheeTang20K.
Verilog
16
star
4

crash_analysis

Analysis for the May 7th, 2021, Shaoguan Guangdong crash.
Python
15
star
5

Verilog_TCP

Highly specialized TCP module. Simple and high-performance. No ARP support.
SystemVerilog
7
star
6

Downloader

Downloader by CY68013
5
star
7

verilog_UDP

SystemVerilog
5
star
8

Route_Planning

MATLAB
3
star
9

LicheeTang25k_SDRAM

SDRAM controller for LicheeTang25k
SystemVerilog
3
star
10

Super-Scalar-RV32

Learn to design super scalar processors and use advanced HDLs. Design from scratch.
Verilog
2
star
11

locker

This is a py program which may detect the USB device and do sth.(lock, etc.)
Python
2
star
12

USB_Clock_Generator

A Clock Generator with USB Type-C, based on CH551 and MS5351 (Compatible with Si5351)
C
2
star
13

Mobile-Heartrate-Monitor

mobile heartrate monitor on AT32F403A with RT-Thread
C
2
star
14

HDW_6807

Drive HDW_6807 (KS0108) with STM32F103
C
1
star
15

LicheeTang25k_VexRV_micro

Verilog
1
star