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General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.DeepFakeVoice
from CorentinJ / Real-Time-Voice-CloningLicheeTang20K_DDR_Test
The DDR Test Firmware for LicheeTang20K.crash_analysis
Analysis for the May 7th, 2021, Shaoguan Guangdong crash.Verilog_TCP
Highly specialized TCP module. Simple and high-performance. No ARP support.Downloader
Downloader by CY68013verilog_UDP
Route_Planning
LicheeTang25k_SDRAM
SDRAM controller for LicheeTang25kSuper-Scalar-RV32
Learn to design super scalar processors and use advanced HDLs. Design from scratch.locker
This is a py program which may detect the USB device and do sth.(lock, etc.)Mobile-Heartrate-Monitor
mobile heartrate monitor on AT32F403A with RT-ThreadHDW_6807
Drive HDW_6807 (KS0108) with STM32F103LicheeTang25k_VexRV_micro
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