ZiyangYE/General-Slow-DDR3-Interface ZiyangYE/General-Slow-DDR3-Interface

  • Stars
    star
    34
  • Rank 762,662 (Top 16 %)
  • Language Verilog
  • License
    BSD 3-Clause "New...
  • Created over 2 years ago
  • Updated 5 months ago
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ZiyangYE/General-Slow-DDR3-Interface
github

ZiyangYE

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Repository Details

A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.

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