Berin Martini (@bmartini)
github

bmartini

Twitter logo Share LinkedIn logo Share Facebook logo Share
  • Stars
    star
    269
  • Global Rank 97,271 (Top 4 %)
  • Followers 70
  • Following 1
  • Registered almost 15 years ago
  • Most used languages
    Verilog     36.8 %
    C
         21.1 %
    Python
         21.1 %
    SystemVerilog     10.5 %
    Shell
         5.3 %
    C++
         5.3 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 24,596
  • Country Ranking
    Verilog     39
    SystemVerilog     221
    C
         2,162

Top repositories

1

zynq-axis

Hardware, Linux Driver and Library for the Zynq AXI DMA interface
Verilog
98
star
2

zynq-xdma

Linux Driver for the Zynq FPGA DMA engine
C
86
star
3

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.
Verilog
40
star
4

cnn-coprocessor

Convolutional Neural Networks Coprocessor
Verilog
10
star
5

vpw-testbench

Verilator Python Wrapper and testbench framework
Python
6
star
6

zynq-uflow

Linux UIO Driver for the Zynq AXI4Lite interface
C
5
star
7

vdent

Verilog Indenter. Simple indent program for Verilog source code. Trims end of line white space and indents lines based on nested depth of code blocks.
C++
4
star
8

zedboard-vivado-loopback

Zedboard loopback Vivado project for use with the zynq-xdma driver
Verilog
3
star
9

worker-threads

Simple boss & long lived worker pthread example
C
3
star
10

skid-buffer

Verilog Skid Buffer
Verilog
3
star
11

cpvdep

Copy Verilog source files and all 'included' dependencies.
Shell
2
star
12

system-rdl-generator

Simple examples of SystemRDL generators
Python
2
star
13

bitter-build-utility

Build utility for working with Xilinx tools on the command line
Python
1
star
14

hdl-axi-common

Common HDL AXI modules
SystemVerilog
1
star
15

verilog-cdc

Selection of Clock Domain Crossing modules
SystemVerilog
1
star
16

fifo-in-c

FIFO written in C of fixed size that will drop data if full
C
1
star
17

zedboard-simple-loopback

Zedboard loopback PlanAhead project for use with the zynq-xdma driver
Verilog
1
star
18

stream-filter

Streaming Convolutional Filter
Verilog
1
star
19

streaming-convolution

A streaming convolution engine
Python
1
star