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HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.64-bit-Universal-Floating-Point-ISA-Compute-Engine
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgineSYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.RISC-V-SYMPL-Hybrid-Floating-Point-ISA-Compute-Engine
New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.Conscious_Gate_Transistor
Conscious Gate Transistor for creating conscious computers and machines. Provisional Patent Application with OpenSCAD 3D models.SYMPL_IEEE754-2019_ISA
SYMPL IEEE 754-2019 Instruction Set Architecture Compute EngineIEEE-754-2008-Fused-Multiply-Add
Fully pipelined IEEE 754-2008 "universal" Fused Multiply-Add operator in Verilog RTL directly accepts H=20 decimalCharacterSequence, binary16, binary32 and binary64 formatted numbers as operands.CustomASM-for-SYMPL-ISA
SYMPL ISA Rule table for open-source CustomASM cross-assembler.IEEE-754-2008-H-20-convertToDecimalCharacter
Fully pipelined IEEE 754-2008 H=20 "convertToDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAsIEEE-754-2008-H-20-convertFromDecimalCharacter
Fully pipelined IEEE 754-2008 H=20 "convertFromDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAsIEEE-754-2008_ISA_CPU
World's first and only 64-bit IEEE 754-2008 Instruction Set Architecture CPU implements "all" mandated operations in hardware with a single instruction per operation.Love Open Source and this site? Check out how you can help us