Jerry D. Harthcock (@jerry-D)
  • Stars
    star
    129
  • Global Rank 172,474 (Top 6 %)
  • Followers 29
  • Registered almost 10 years ago
  • Most used languages
    Verilog
    50.0 %
    OpenSCAD
    16.7 %
    Rust
    16.7 %
    Assembly
    16.7 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 42,084
  • Country Ranking
    Verilog
    67
    OpenSCAD
    142
    Assembly
    794
    Rust
    7,595

Top repositories

1

HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine

HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
Verilog
51
star
2

64-bit-Universal-Floating-Point-ISA-Compute-Engine

RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
Verilog
22
star
3

SYMPL-GP-GPU-Compute-Engines

Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
22
star
4

RISC-V-SYMPL-Hybrid-Floating-Point-ISA-Compute-Engine

New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.
Verilog
10
star
5

Conscious_Gate_Transistor

Conscious Gate Transistor for creating conscious computers and machines. Provisional Patent Application with OpenSCAD 3D models.
OpenSCAD
6
star
6

SYMPL_IEEE754-2019_ISA

SYMPL IEEE 754-2019 Instruction Set Architecture Compute Engine
Assembly
6
star
7

IEEE-754-2008-Fused-Multiply-Add

Fully pipelined IEEE 754-2008 "universal" Fused Multiply-Add operator in Verilog RTL directly accepts H=20 decimalCharacterSequence, binary16, binary32 and binary64 formatted numbers as operands.
4
star
8

CustomASM-for-SYMPL-ISA

SYMPL ISA Rule table for open-source CustomASM cross-assembler.
Rust
2
star
9

IEEE-754-2008-Emulator

Universal IEEE 754-2008 Floating-Point Emulator for Xilinx and Altera FPGAs. Implements in hardware the entire (required) repertoire for half, single and double-precision binary formats, but with range limited to 5 bits and precision to 10 bits. If you require greater range and precision, contact me.
2
star
10

IEEE-754-2008-H-20-convertToDecimalCharacter

Fully pipelined IEEE 754-2008 H=20 "convertToDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
1
star
11

IEEE-754-2008-H-20-convertFromDecimalCharacter

Fully pipelined IEEE 754-2008 H=20 "convertFromDecimalCharacter" binary64 operator for Xilinx UltraScale FPGAs
1
star
12

IEEE-754-2008_ISA_CPU

World's first and only 64-bit IEEE 754-2008 Instruction Set Architecture CPU implements "all" mandated operations in hardware with a single instruction per operation.
1
star