iammituraj/pequeno_riscv

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Rank 879,276 (Top 18 %)
Language SystemVerilog
License
Other
Created 10 months ago
Updated 3 months ago

iammituraj/pequeno_riscv

iammituraj

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Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

FIFOs

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

pqr5asm

PQR5ASM is a RISC-V Assembler compliant with RV32I

apb

APB master and slave developed in RTL.

debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

LIFO-Stack

Register-based LIFO aka Stack designed in Verilog/System Verilog.

reset_and_cdc_synchronizers

Reset and CDC synchronizers developed in Verilog/System Verilog.

gcd_calculator

GCD calculator with APB Slave interface.