Mitu Raj (@iammituraj)
github

iammituraj

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  • Stars
    star
    86
  • Global Rank 230,854 (Top 8 %)
  • Followers 54
  • Following 7
  • Registered over 5 years ago
  • Most used languages
    SystemVerilog     88.9 %
    Python
         11.1 %
  • Location 🇮🇳 India
  • Country Total Rank 29,012
  • Country Ranking
    SystemVerilog     2
    Python
         7,171

Top repositories

1

pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
SystemVerilog
28
star
2

FIFOs

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
SystemVerilog
14
star
3

skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
SystemVerilog
12
star
4

pqr5asm

PQR5ASM is a RISC-V Assembler compliant with RV32I
Python
11
star
5

apb

APB master and slave developed in RTL.
SystemVerilog
7
star
6

debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.
SystemVerilog
5
star
7

LIFO-Stack

Register-based LIFO aka Stack designed in Verilog/System Verilog.
SystemVerilog
4
star
8

reset_and_cdc_synchronizers

Reset and CDC synchronizers developed in Verilog/System Verilog.
SystemVerilog
3
star
9

gcd_calculator

GCD calculator with APB Slave interface.
SystemVerilog
2
star