• Stars
    star
    57
  • Rank 522,947 (Top 11 %)
  • Language
    Python
  • License
    Other
  • Created about 3 years ago
  • Updated 7 months ago

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Repository Details

LiteX development baseboards arround the SQRL Acorn.

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daisho

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litex_m2sdr

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liteiclink

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pcie_analyzer

PCIe analyzer experiments
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litejesd204b

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litex_vexriscv_smp_test

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xtrx_julia

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litex_rp2040_pmod_test

Test of a RP2040 PMOD attached to a LiteX SoC.
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litex_verilog_axi_test

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litesata_axiom

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fk33_hbm2_test

HBM2 integration test on FK33 with LiteX
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litex_hw_ci

LiteX Hardware CI tests.
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litex_vexriscv_smp_usb_host_test

Integration test with SpinalHDL's OHCI USB Host core and LiteX/VexRiscv-SMP.
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litex_neorv32_test

NEORV32 integration test with LiteX
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litex_playground

Small LiteX related projects that have been or could be useful...
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litex_soc_gen_test

Test of LiteX standalone SoC generator.
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litepcie_ptm_test

LitePCIe PTM support / test repo.
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tapcfg

tapcfg
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litex_naxriscv_test

NaxRiscv integration test with LiteX
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litex_limesdr_mini_v2_test

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litex_openwrt_test

Test of OpenWRT on LiteX SoCs.
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betrusted_soc_power_tests

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vhdl2doc

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litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
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litex_mister_test

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mbd_poc

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litedram_halfrate

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acorn_pcie_compute_test

PCIe compute test on Acorn CLE 215+.
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litedram_ddr4_mig_phy_test

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litex_thunderscope_test

Test of LiteX component for ThunderScope project.
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litex_verilog_axis_test

Integration test of Verilog AXI Stream modules (https://github.com/alexforencich/verilog-axis) with LiteX.
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43

litex_xtrx

XTRX LiteX/LitePCIe based alternative Gateware/Software.
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44

litex_64bit_addressing_test

Test/PoC of 64-bit addressing in LiteX.
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