@enjoy-digital
github

enjoy-digital

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  • Stars
    star
    4,963
  • Global Rank 5,281 (Top 0.2 %)
  • Followers 1,143
  • Registered over 12 years ago
  • Most used languages
    Python
         71.8 %
    C
         12.8 %
    Verilog     10.3 %
    JavaScript
         2.6 %
    VHDL     2.6 %
  • Location πŸ‡«πŸ‡· France
  • Country Total Rank 191
  • Country Ranking
    Verilog     2
    C
         14
    VHDL     39
    Python
         67
    JavaScript
         8,517

Top repositories

1

litex

Build your hardware, easily!
C
2,699
star
2

litepcie

Small footprint and configurable PCIe core
Python
438
star
3

litedram

Small footprint and configurable DRAM core
Python
360
star
4

liteeth

Small footprint and configurable Ethernet core
Python
192
star
5

usb3_pipe

USB3 PIPE interface for Xilinx 7-Series
Verilog
178
star
6

litescope

Small footprint and configurable embedded FPGA logic analyzer
Python
157
star
7

pcie_screamer

PCIe Screamer - TLPs experiments...
C
155
star
8

litesata

Small footprint and configurable SATA core
Python
120
star
9

litesdcard

Small footprint and configurable SDCard core
Python
107
star
10

colorlite

Take control of your Colorlight FPGA board with LiteX/LiteEth :)
Python
90
star
11

daisho

Test of the USB3 IP Core from Daisho on a Xilinx device
Verilog
78
star
12

liteiclink

Small footprint and configurable Inter-Chip communication cores
Python
51
star
13

litex-acorn-baseboard

LiteX development baseboards arround the SQRL Acorn.
Python
47
star
14

pcie_analyzer

PCIe analyzer experiments
Python
42
star
15

litejesd204b

Small footprint and configurable JESD204B core
Python
36
star
16

litex_vexriscv_smp_test

VexRiscv-SMP integration test with LiteX.
Verilog
24
star
17

xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing
C
21
star
18

litex_rp2040_pmod_test

Test of a RP2040 PMOD attached to a LiteX SoC.
Python
21
star
19

thunderscope

LiteX based FPGA gateware for Thunderscope.
Python
19
star
20

litex_verilog_axi_test

Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
Python
13
star
21

litesata_axiom

Python
12
star
22

fk33_hbm2_test

HBM2 integration test on FK33 with LiteX
Python
9
star
23

litex_vexriscv_smp_usb_host_test

Integration test with SpinalHDL's OHCI USB Host core and LiteX/VexRiscv-SMP.
Python
6
star
24

litex_neorv32_test

NEORV32 integration test with LiteX
VHDL
6
star
25

litex_hw_ci

LiteX Hardware CI tests.
Python
6
star
26

litex_playground

Small LiteX related projects that have been or could be useful...
C
5
star
27

litex_soc_gen_test

Test of LiteX standalone SoC generator.
Python
4
star
28

litex_naxriscv_test

NaxRiscv integration test with LiteX
Python
4
star
29

tapcfg

tapcfg
C
4
star
30

litepcie_ptm_test

LitePCIe PTM support / test repo.
Python
3
star
31

vhdl2doc

JavaScript
3
star
32

litex_limesdr_mini_v2_test

LiteX alternative SoC/Gateware for the LimeSDR Mini 2.0
Python
2
star
33

betrusted_soc_power_tests

Python
2
star
34

mbd_poc

Python
1
star
35

litedram_halfrate

Python
1
star
36

acorn_pcie_compute_test

PCIe compute test on Acorn CLE 215+.
Python
1
star
37

litedram_ddr4_mig_phy_test

LiteDRAM Hybrid with DDR4 PHY
Python
1
star
38

litex_thunderscope_test

Test of LiteX component for ThunderScope project.
Python
1
star
39

litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.
Verilog
1
star