enjoy-digital/colorlite enjoy-digital/colorlite

  • Stars
    star
    95
  • Rank 354,083 (Top 7 %)
  • Language
    Python
  • License
    BSD 2-Clause "Sim...
  • Created over 4 years ago
  • Updated over 1 year ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
enjoy-digital/colorlite
github

enjoy-digital

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Take control of your Colorlight FPGA board with LiteX/LiteEth :)

More Repositories

1

litex

Build your hardware, easily!
C
2,962
star
2

litepcie

Small footprint and configurable PCIe core
Python
476
star
3

litedram

Small footprint and configurable DRAM core
Python
378
star
4

liteeth

Small footprint and configurable Ethernet core
Python
212
star
5

usb3_pipe

USB3 PIPE interface for Xilinx 7-Series
Verilog
199
star
6

litescope

Small footprint and configurable embedded FPGA logic analyzer
Python
169
star
7

pcie_screamer

PCIe Screamer - TLPs experiments...
C
164
star
8

litesata

Small footprint and configurable SATA core
Python
126
star
9

litesdcard

Small footprint and configurable SDCard core
Python
110
star
10

daisho

Test of the USB3 IP Core from Daisho on a Xilinx device
Verilog
85
star
11

litex_m2sdr

LiteX based M2 SDR FPGA board.
C
58
star
12

litex-acorn-baseboard

LiteX development baseboards arround the SQRL Acorn.
Python
57
star
13

liteiclink

Small footprint and configurable Inter-Chip communication cores
Python
54
star
14

pcie_analyzer

PCIe analyzer experiments
Python
45
star
15

litejesd204b

Small footprint and configurable JESD204B core
Python
40
star
16

litex_vexriscv_smp_test

VexRiscv-SMP integration test with LiteX.
Verilog
24
star
17

xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing
C
24
star
18

litex_rp2040_pmod_test

Test of a RP2040 PMOD attached to a LiteX SoC.
Python
24
star
19

thunderscope

LiteX based FPGA gateware for Thunderscope.
Python
22
star
20

litex_verilog_axi_test

Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
Python
15
star
21

litesata_axiom

Python
12
star
22

fk33_hbm2_test

HBM2 integration test on FK33 with LiteX
Python
9
star
23

litex_hw_ci

LiteX Hardware CI tests.
Python
8
star
24

litex_vexriscv_smp_usb_host_test

Integration test with SpinalHDL's OHCI USB Host core and LiteX/VexRiscv-SMP.
Python
7
star
25

litex_neorv32_test

NEORV32 integration test with LiteX
VHDL
6
star
26

litex_playground

Small LiteX related projects that have been or could be useful...
C
5
star
27

litex_soc_gen_test

Test of LiteX standalone SoC generator.
Python
5
star
28

litepcie_ptm_test

LitePCIe PTM support / test repo.
Python
5
star
29

tapcfg

tapcfg
C
5
star
30

litex_naxriscv_test

NaxRiscv integration test with LiteX
Python
4
star
31

litex_limesdr_mini_v2_test

LiteX alternative SoC/Gateware for the LimeSDR Mini 2.0
Python
3
star
32

litex_openwrt_test

Test of OpenWRT on LiteX SoCs.
C
3
star
33

betrusted_soc_power_tests

Python
3
star
34

vhdl2doc

JavaScript
3
star
35

litex_agilex5_test

Initial Test/Support of LiteX on Intel Agilex5 FPGAs.
Python
3
star
36

litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.
Verilog
2
star
37

mbd_poc

Python
1
star
38

litedram_halfrate

Python
1
star
39

acorn_pcie_compute_test

PCIe compute test on Acorn CLE 215+.
Python
1
star
40

litedram_ddr4_mig_phy_test

LiteDRAM Hybrid with DDR4 PHY
Python
1
star
41

litex_thunderscope_test

Test of LiteX component for ThunderScope project.
Python
1
star
42

litex_verilog_axis_test

Integration test of Verilog AXI Stream modules (https://github.com/alexforencich/verilog-axis) with LiteX.
Python
1
star
43

litex_xtrx

XTRX LiteX/LitePCIe based alternative Gateware/Software.
C++
1
star
44

litex_64bit_addressing_test

Test/PoC of 64-bit addressing in LiteX.
Python
1
star