Bucknalla/sigfox-hidnseek-tutorial

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Bucknalla/sigfox-hidnseek-tutorial

Bucknalla

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Sigfox tutorial for getting started with the Hidnseek GPS Locator

micropython-i2c-lcd

🖥 MicroPython Library for I2C 2x16 LCD Screens

balena-pycom-ota

📶 Over the Air Update Manager for balena devices to control Pycom devices

lopy-raspberrypi

🎮 Use a Raspberry Pi to control a LoPy over UART

ip_cores

Verilog IP Cores & Tests

sigfox-python-flask

Example of a quick and easy Python Flask Server utilising Sigfox's callback capability

attendee-tool-mlh

es3b2

Lab notes for ES3B2 (ES2E3)- Digital Systems Design

efm32-arduino-core

Arduino Core for Silicon Labs EFM32 Family

ES3F1_Labs

Lab Content for ES3F1 High Performance Embedded Systems Design

ip-cores

⚙️ IP Cores for Xilinx FPGA Devices

animal-crossing-player

Console Python Script to play animal crossing (wild world) songs according to the hour and day.

name-block

Tired of boring balena device names? Why not let us choose!

OFDM_Verilog

Example of OFDM in Python and Verilog

hidnseek-dev

📄 HidnSeek Documentation for use as a Sigfox Development Kit

lepton-core

FLIR Lepton Fusesoc Core (Verilog)

zynq-documentation

Introduction to Xilinx Zynq SoC Platform

sigfox-cli

ultra96-gpio-mezzanine

96Board compliant mezzanine for the Ultra96 ZynqMP board

balena-fin-sleep

BalenaFin Coprocessor sleep example

verilog-snippets

Verilog Snippets for VSCode

MicroPython-3-Axis-Accelerometer

MIcroPython Library for Various Accelerometers #MicroPython

zynq-ip-cores

IP cores for Xilinx Zynq SoC

chip_8_hdl

Chip 8 Architecture in Verilog

ultra96-dna

Get UUID from DNA Registers on Ultra96

i2c-core

parametric_qam

Parametrically Controlled Quadarature Modulation Encoder

gnu_radio

GNU Radio Projects

BitPiRat-FPGA

FPGA support for balena-based BitPiRat

ice-samd-feather

ICE40HX + SAMD21 Feather Board

engineering-scripts

A collection of useful tools for engineering

practice-c

Repository of practice code for improving C knowledge

arduino-tutorials

Warwick University - School of Engineering - Arduino Tutorials

ultra96-csi-mezzanine

Mezzanine for Ultra96 CSI Camera

axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

AD9361_ZyCAP

PL Layer Controls for the AD9361 RF Front End

warc_fusesoc

WARC Open Fusesoc Cores Repository

zigbee-balena

Zigbee Coordinator and Firmware Management Fleet

MyHDL_Snippets

Python MyHDL Snippets

coprocessor-spi-flash

ice-projects

Collection of Verilog Projects synthesizable for the Lattice iCEStick using OSS Toolchain