Alex Bucknall (@Bucknalla)
github

Bucknalla

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  • Stars
    star
    165
  • Global Rank 143,168 (Top 5 %)
  • Followers 138
  • Following 39
  • Registered over 11 years ago
  • Most used languages
    Python
         36.7 %
    VHDL     13.3 %
    Verilog     13.3 %
    Tcl     10.0 %
    C
         6.7 %
    C++
         6.7 %
    HTML
         3.3 %
    Arduino     3.3 %
    JavaScript
         3.3 %
    Eagle     3.3 %
  • Location 🇬🇧 United Kingdom
  • Country Total Rank 6,446
  • Country Ranking
    VHDL     21
    Tcl     26
    Eagle     41
    Verilog     52
    Arduino     80
    C
         2,166
    Python
         2,243
    HTML
         4,644
    C++
         4,743

Top repositories

1

micropython-i2c-lcd

🖥 MicroPython Library for I2C 2x16 LCD Screens
Python
23
star
2

balena-pycom-ota

📶 Over the Air Update Manager for balena devices to control Pycom devices
Python
13
star
3

lopy-raspberrypi

🎮 Use a Raspberry Pi to control a LoPy over UART
Python
12
star
4

ip_cores

Verilog IP Cores & Tests
VHDL
11
star
5

sigfox-python-flask

Example of a quick and easy Python Flask Server utilising Sigfox's callback capability
Arduino
9
star
6

attendee-tool-mlh

Python
5
star
7

es3b2

Lab notes for ES3B2 (ES2E3)- Digital Systems Design
Verilog
4
star
8

efm32-arduino-core

Arduino Core for Silicon Labs EFM32 Family
C
4
star
9

ES3F1_Labs

Lab Content for ES3F1 High Performance Embedded Systems Design
Tcl
4
star
10

ip-cores

⚙️ IP Cores for Xilinx FPGA Devices
VHDL
4
star
11

sigfox-hidnseek-tutorial

Sigfox tutorial for getting started with the Hidnseek GPS Locator
4
star
12

animal-crossing-player

Console Python Script to play animal crossing (wild world) songs according to the hour and day.
Python
4
star
13

name-block

Tired of boring balena device names? Why not let us choose!
JavaScript
3
star
14

OFDM_Verilog

Example of OFDM in Python and Verilog
Python
3
star
15

hidnseek-dev

📄 HidnSeek Documentation for use as a Sigfox Development Kit
Eagle
3
star
16

lepton-core

FLIR Lepton Fusesoc Core (Verilog)
VHDL
2
star
17

zynq-documentation

Introduction to Xilinx Zynq SoC Platform
HTML
2
star
18

sigfox-cli

Python
2
star
19

ultra96-gpio-mezzanine

96Board compliant mezzanine for the Ultra96 ZynqMP board
2
star
20

balena-fin-sleep

BalenaFin Coprocessor sleep example
Python
2
star
21

verilog-snippets

Verilog Snippets for VSCode
2
star
22

MicroPython-3-Axis-Accelerometer

MIcroPython Library for Various Accelerometers #MicroPython
C++
1
star
23

zynq-ip-cores

IP cores for Xilinx Zynq SoC
VHDL
1
star
24

chip_8_hdl

Chip 8 Architecture in Verilog
Verilog
1
star
25

ultra96-dna

Get UUID from DNA Registers on Ultra96
Tcl
1
star
26

i2c-core

Verilog
1
star
27

parametric_qam

Parametrically Controlled Quadarature Modulation Encoder
1
star
28

gnu_radio

GNU Radio Projects
Python
1
star
29

BitPiRat-FPGA

FPGA support for balena-based BitPiRat
1
star
30

ice-samd-feather

ICE40HX + SAMD21 Feather Board
1
star
31

engineering-scripts

A collection of useful tools for engineering
Python
1
star
32

practice-c

Repository of practice code for improving C knowledge
C
1
star
33

arduino-tutorials

Warwick University - School of Engineering - Arduino Tutorials
C++
1
star
34

ultra96-csi-mezzanine

Mezzanine for Ultra96 CSI Camera
Python
1
star
35

axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files
1
star
36

AD9361_ZyCAP

PL Layer Controls for the AD9361 RF Front End
1
star
37

warc_fusesoc

WARC Open Fusesoc Cores Repository
Tcl
1
star
38

zigbee-balena

Zigbee Coordinator and Firmware Management Fleet
1
star
39

MyHDL_Snippets

Python MyHDL Snippets
1
star
40

coprocessor-spi-flash

1
star
41

ice-projects

Collection of Verilog Projects synthesizable for the Lattice iCEStick using OSS Toolchain
Verilog
1
star