Discover @funningboy Open Source projects

sean (@funningboy)

funningboy

Stars
356
Global Rank 77,490 (Top 3 %)
Followers 59
Following 12
Registered about 14 years ago
Most used languages

Perl
41.7 %

C++
16.7 %

Python
16.7 %

C
12.5 %

Assembly
4.2 %

Jupyter Notebook
4.2 %

Verilog 4.2 %
Location 🇹🇼 Taiwan
Country Total Rank 430
Country Ranking

Verilog 1

Perl
19

Assembly
33

C
159

C++
173

Jupyter Notebook
322

Python
533

uvm_axi

uvm AXI BFM(bus functional model)

pyvpi_example

use pivpi to drive testbench event

smtdv

make your verilog DUT test more smart

carCV

vim

UVM/systemverilog/verilog/python VIM IDE

remoteChat

remote chat example based on webrtc opencv flask zeroMQ

scrapy_giant

taiwan stock crawler/analysis

Jupyter Notebook

xbus

an easy bus verification example based on UVM/SV framework

remoteCV

remote video process via OpenCV + raspberry pi

soc

demo how to use HW/SW co-verification

openCV_myHDL

build up a co-sim verification env via openCV and myHDL

DDE

get the finance data from web or DDE server

veri_2_graph

gate level verilog 2 graph viewer

finance

get the finance statistic data from history data

BIST

Pattern Generation for Logic BIST

example_MyHDL

example code for MyHDL project

profit-analysis

a finance analysis tool for profits

SOC_c_model

hardware emulators in system level

iso_cell

Isolation Cell Insertion for Low Power Design

co_syn

co-syn with Google server @ perl

XVerilog

pylive555

import live555 lib to python

SOC_SystemC_model

SOC_SystemC_model

hg_lvl_syn

high level synthesis with SOC

3D_pwrIC

3D IC Design Partitioning with Power Consideration

iso_cell_rc1

Structural Checking of Voltage-Island and Power Gating Low-Power Logic Design