funningboy/profit-analysis funningboy/profit-analysis

  • Stars
    star
    2
  • Language
    Perl
  • Created about 14 years ago
  • Updated about 14 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
funningboy/profit-analysis
github

funningboy

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

a finance analysis tool for profits

More Repositories

1

uvm_axi

uvm AXI BFM(bus functional model)
Verilog
201
star
2

pyvpi_example

use pivpi to drive testbench event
C
20
star
3

smtdv

make your verilog DUT test more smart
C++
18
star
4

carCV

carCV
Python
18
star
5

vim

UVM/systemverilog/verilog/python VIM IDE
14
star
6

remoteChat

remote chat example based on webrtc opencv flask zeroMQ
Python
9
star
7

scrapy_giant

taiwan stock crawler/analysis
Jupyter Notebook
8
star
8

xbus

an easy bus verification example based on UVM/SV framework
C++
5
star
9

remoteCV

remote video process via OpenCV + raspberry pi
Python
4
star
10

soc

demo how to use HW/SW co-verification
C
4
star
11

openCV_myHDL

build up a co-sim verification env via openCV and myHDL
Python
3
star
12

DDE

get the finance data from web or DDE server
Perl
3
star
13

veri_2_graph

gate level verilog 2 graph viewer
Perl
2
star
14

finance

get the finance statistic data from history data
Perl
2
star
15

BIST

Pattern Generation for Logic BIST
Perl
2
star
16

example_MyHDL

example code for MyHDL project
Assembly
2
star
17

SOC_c_model

hardware emulators in system level
Perl
1
star
18

iso_cell

Isolation Cell Insertion for Low Power Design
Perl
1
star
19

co_syn

co-syn with Google server @ perl
Perl
1
star
20

XVerilog

DFG synthesis
C
1
star
21

pylive555

import live555 lib to python
C++
1
star
22

SOC_SystemC_model

SOC_SystemC_model
1
star
23

hg_lvl_syn

high level synthesis with SOC
Perl
1
star
24

3D_pwrIC

3D IC Design Partitioning with Power Consideration
Perl
1
star
25

iso_cell_rc1

Structural Checking of Voltage-Island and Power Gating Low-Power Logic Design
C++
1
star