xjtuiair-cag/Vscale_plus

Stars
10
Rank 1,807,489 (Top 36 %)
Language Verilog
Created about 5 years ago
Updated about 5 years ago

xjtuiair-cag/Vscale_plus

xjtuiair-cag

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

A 3-stage in-order single-scalar RISC-V processor

XJTU-Tripler

XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

Matterhorn

A novel general neuromorphic computing framework based on PyTorch.

Open-HiPU200

HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.

gem5_dda

A gem5 experimental repo in order to explore Data-dependent Access (DDA).

c910-fpga

An FPGA project of a simple SOC witn Xuantie c906

xjtucag-benchmarks

dmp

Dmp: differential matching prefetcher