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Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.yarvi
Yet Another RISC-V Implementationfpgammix
Partial implementation of Knuth's MMIX processor (FPGA softcore)yari
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.Paperlike-Raspberry-Pi-4
How to use a Dasung Paperlike HD-F, HD-FT, and Paperlike 253 with Raspberry Pi 4 [and other hosts?]virtual-nascom
SDL-based Nascom 2 emulatorBeMicro-CV
A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CVspleentt-5x8-font
Tiny 5x8 bitmap font based on spleen and creep, useful for low-resolution displaysverilator-demo
A very simple example of how to use VerilatorOrangeCrab_Hello
Simple OrangeCrab Verilog design using LED and serial IOexpjit3
Proof of concept dynamic code generationdirac-spec-errata
Bug-fixed version of the official specification of the Dirac wavelet based video codecgdb-duel
DUEL - A high level language for debugging C programs (by Michael Golan)bemicro_cva9_jtaguart
Small example design for BeMicro CV-A9 using JTAGUART and LEDsverilog-sim-bench
Verilog simulation workload extracted from Reduceronbp
Fun with branch predictorsrust-verilog-cosim
Small example of how to co-simulate a Rust model against a Verilog implementation, using Verilator0toasic
Stuff I did for Matt Venn's Zero-to-ASIC coursetinyc-in-rust
Marc Feeley's Tiny-C compiler, rewritten in Rustjsnascom
Nascom 2 emulator in the browseryarvi3
no-time-for-squares
VGA Clock Design For Tiny Tapeout 05lisp
A version of John McCarthy's tiny Lisp (in C) with added CDR-codingmultisim
MultiSim is Yet Another CPU Simulator which purpose in life is to allow easy experimentation with various implementation strategies, such as superscalar in-order, sscalar out-of-order, speculative sscalar out-of-order, etc.kbe
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