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yosys-examples
Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)libpnmio
C library for reading and writing PNM (PBM/PGM/PPM) and PFM images.kvcordic
Multi-function, universal, fixed-point CORDICfixed_extensions
VHDL fixed-point arithmetic extensions packagegvizparse
Standalone lex/yacc parser for the Graphviz (www.graphviz.org) formatcomplexpack
complexpack is a complex arithmetic package written in VHDL.kdiv
kdiv is a generator of routines for optimized division by an integer constant.kmul
kmul is a generator of routines for optimized multiplication by an integer constant.color_maker-s3esk
A simple VGA output tester for the Xilinx Spartan-3E starter kit board.ratpack
VHDL rational arithmetic packageinterval
Interval arithmetic API for ANSI Cmu0
HDL models and programming tools for the educational MU0 processortoy
Assembler and simulator for the Princeton TOY machinepde2hw
FPGA-based hardware prototypes in Processingmpintpack
Multi-precision integer arithmetic in VHDLmprfgen
Multi-port register file generatorvhdl-examples
VHDL examples for simulation and synthesisxopreplace
Machine-SUIF pass for replacing a function call by a SUIFvm operatorloopstr
Natural loop analysis pass for Machine-SUIFdlx
DLX functional model for ArchCrasalghul
The RASter (graphics) ALGorithms HULkbstest-s3esk
A buttons, switches and LEDs tester for the Xilinx Spartan-3E starter kit board.Love Open Source and this site? Check out how you can help us