maltanar/brevitas_cnv_lfc

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7
Rank 2,294,772 (Top 46 %)
Language
Python
License
MIT License
Created about 5 years ago
Updated over 4 years ago

maltanar/brevitas_cnv_lfc

maltanar

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fpga-tidbits

Chisel components for FPGA projects

axi-in-chisel

Examples for creating AXI-interfaced peripherals in Chisel

qnn-inference-examples

Jupyter notebook examples on image classification with quantized neural networks

Jupyter Notebook

rosetta

Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ

gemmbitserial

Fast matrix multiplication for few-bit integer matrices on CPUs.

fpga-booleanring-bfs

Hybrid BFS on Xilinx Zynq

systemc-chisel-tools

A collection of tools for working with Chisel-generated hardware in SystemC

spmvaccsim

A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.

spmv-vector-cache

A Vector Caching Scheme for Streaming FPGA SpMV Accelerators

seyrek

A framework for generating semiring-based sparse graph accelerators for FPGAs

wolverine-chisel-examples

Chisel wrappers and examples for Convey's Wolverine FPGA accelerators

tdt4255-hostcomm

Tools for the NTNU TDT4255 (Computer Design) course laboratory

colmajor-spmv-backend

Source code that accompanies the paper "An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators"

watchntouch

Automatically exported from code.google.com/p/watchntouch

zedboard-cheetah

Utilities for transferring large files into the ZedBoard over ethernet for bare-bones projects

equine-health-monitor-gdp12

Automatically exported from code.google.com/p/equine-health-monitor-gdp12