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fpga-tidbits
Chisel components for FPGA projectsaxi-in-chisel
Examples for creating AXI-interfaced peripherals in Chiselqnn-inference-examples
Jupyter notebook examples on image classification with quantized neural networksrosetta
Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQgemmbitserial
Fast matrix multiplication for few-bit integer matrices on CPUs.fpga-booleanring-bfs
Hybrid BFS on Xilinx Zynqsystemc-chisel-tools
A collection of tools for working with Chisel-generated hardware in SystemCspmvaccsim
A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.spmv-vector-cache
A Vector Caching Scheme for Streaming FPGA SpMV Acceleratorsbrevitas_cnv_lfc
seyrek
A framework for generating semiring-based sparse graph accelerators for FPGAswolverine-chisel-examples
Chisel wrappers and examples for Convey's Wolverine FPGA acceleratorstdt4255-hostcomm
Tools for the NTNU TDT4255 (Computer Design) course laboratorycolmajor-spmv-backend
Source code that accompanies the paper "An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators"zedboard-cheetah
Utilities for transferring large files into the ZedBoard over ethernet for bare-bones projectsequine-health-monitor-gdp12
Automatically exported from code.google.com/p/equine-health-monitor-gdp12Love Open Source and this site? Check out how you can help us