Discover m1geo/Pi5-Artix-FPGA-Hat Open Source project

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Language Verilog
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Created 12 months ago
Updated 8 months ago

m1geo

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An AMD/Xilinx Artix 50T FPGA on a Pi5 Hat with PCIe and GPIO interconnects as well as SPI programming

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A crude reverse engineering of the Pi5 PCIe connector & potential breakout boards.

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A simple and crude CIC filter implementation in Python3 for learning purposes

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MAX6921_VFD_GPS_Clock

Clock that uses TinyGPS to crack GPS strings and displays the time/date on 6 statically driven VFD tubes via 3 MAX6921s

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A PCB for four DVSI AMBE-3000R Vocoders for use with WebSDRs/Audio transcoding

DTSCS

Decentralized Time-Synchronized Channel Swapping (DT-SCS) for Ad Hoc Wireless Networks

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Cloudlog-ADIF-Uploader

Python3 based Cloudlog uploader based around adif-io and JSON POST requests to Cloudlog API

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MediaWiki-to-WordPress

MediaWiki to WordPress Converter based on http://www.analogrithems.com/rant/portfolio/mediawiki2wordpress/

Perl

EH_IOT

Energy Harvesting For The Internet-of-Things: Measurements And Probability Models (Testbed and Analysis Code)

MATLAB

arty_hdmi

A simple test pattern on HDMI display

Verilog

ESP8266-Air-Quality-Sensor

An air quality recorder based on an ESP8266, CCS811, BME280 and DHT22 which logs to ThingSpeak

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RigHop

Program to sync frequency hopping with an Icom amateur radio transceiver using an NTP synced PC clock and CI-V

handifinder

KiCad 5.1 design of the HANDI-Finder Project

verilog-snippets

Random snippets of Verilog for others to use

Verilog

UNV

UNV: Content Centric Live Video Streaming System

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JamesSharmanPipelinedCPU

An FPGA implementation of James Sharman's Pipelined CPU: https://www.youtube.com/watch?v=KEwL2P8IGaA

Verilog

frequency-counter

A frequency counter based around Ublox GPS 1PPS, Lattice MachX02 FPGA, Arduino Uno and LCD

HTML

WordClock

A custom WordClock project.

C++

contiki-temperature

Takes measurements from Temperature, Humidity, Visible and IR Light and saves them to flash memory.

IV16-Numitron-Clock

An FPGA based IV-16 Numitron Clock

Verilog

contiki-packet-delivery-ratio

Simple Contiki code for multichannel PDR measurement

arty_vga

A working attempt at 800x600 VGA using an Arty A7 dev board (Artix A7T35 FPGA) with SPI interface and example Arduino code

VHDL

m1geo/Pi5-Artix-FPGA-Hat

m1geo

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