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Steps to install and run on UBUNTU: 1) sudo apt-get install git 2) git clone https://github.com/kunalg123/vsdflow.git 3) cd vsdflow 4) chmod 777 opensource_eda_tool_install.sh 5) ./opensource_eda_tool_install.sh **NOTE for freshers : This has been tested on a fresh UBUNTU installtion **NOTE for experienced UNIX users : It has lot of sudo apt-get and sudo remove commands, so you might want to review before running 6) ./vsdflow spi_slave_design_details.csv 7) ./vsdflow picorv32_design_details.csv Steps to install and run on CENTOS: First login as root using below command (IMPORTANT) su - Then follow below steps 1) sudo yum install git 2) git clone https://github.com/kunalg123/vsdflow.git 3) cd vsdflow 4) chmod 777 opensource_eda_tool_install_centos.sh 5) sudo ./opensource_eda_tool_install_centos.sh **NOTE for freshers : This has been tested on a fresh CENTOS 7 installtion **NOTE for experienced UNIX users : It has lot of sudo yum commands, so you might want to review before running 6) ./vsdflow spi_slave_design_details.csv 7) ./vsdflow picorv32_design_details.csv Steps to test 'vsdflow' on Ubuntu and CENTOS: 1) cd outdir_spi_slave 2) qflow display spi_slave List of Tools installed: 1) Yosys - RTL Synthesis 2) blifFanout - High fanout net (HFN) synthesis 3) graywolf - Placement 4) qrouter - Detailed routing 5) magic - VLSI Layout tool 6) netgen - LVS 7) OpenTimer and OpenSTA - Static timing analysis tool 'vsdflow' is also the best utility ever written for learning EDA based TCL scripting...Very hard to find a tool, with its detailed explanation in form of videos. 'vsdflow' is explained (in detail) in below 2 TCL scripting courses, so you might want to have a look: TCL scripting part 1: https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/ TCL scripting part 2: https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/ This course has gone to a level, where I have heard managers in VLSI industries asking their team to learn TCL only through this course and 'vsdflow'. VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, RISC-V picorv32, and can be further tested for multi-million instance count using hierarchical or glue logic. Some background about VLSI backend is needed for to understand 'vsdflow' operations, so here are 3 important courses: (check with your interviewer and they might recommend these courses): Physical design flow: https://www.udemy.com/vlsi-academy-physical-design-flow/ Static timing analysis - Part 1: https://www.udemy.com/vlsi-academy-sta-checks/ Static timing analysis - Part 2: https://www.udemy.com/vlsi-academy-sta-checks-2/ There you go...Write your first TCL script, learn it from basics to advanced to expert level, apply it from EDA perspective, and you are good to go for your job or interviews.... All the best and happy learning
flipflop_design
This project has files needed to design and characterise flipflopicc2_workshop_collaterals
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainingsriscv_workshop_collaterals
This repository is created for conducting RISC-V 5-day workshopssky130RTLDesignAndSynthesisWorkshop
sky130CircuitDesignWorkshop
device_modelling
Scripts for 1D- and 2D- NMOS device modelling and simulationraven_spi_hierarchical_physical_design
Commit files needed for SPI hierarchical implementationsta_workshop
This repository has all collateral for STA workshoprvmyth
SystemDesignWorkshopCollaterals
ngspice_labs
SPICE simulation labs for workshopavsddac_3v3
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