huyphan168/Sobel-Verilog huyphan168/Sobel-Verilog

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  • Language Verilog
  • Created almost 2 years ago
  • Updated almost 2 years ago
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huyphan168/Sobel-Verilog
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huyphan168

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Repository Details

Implementation of Sobel Operation using AXIS protocol and buffer with 1 MAC.

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