• Stars
    star
    33
  • Rank 783,877 (Top 16 %)
  • Language Verilog
  • License
    MIT License
  • Created over 8 years ago
  • Updated over 8 years ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

More Repositories

1

Forvis_RISCV-ISA-Spec

Formal specification of RISC-V Instruction Set
Haskell
96
star
2

Bluespec_BSV_Tutorial

Bluespec BSV HLHDL tutorial
Bluespec
92
star
3

ICFP2020_Bluespec_Tutorial

Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
HTML
65
star
4

Learn_Bluespec_and_RISCV_Design

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
Verilog
51
star
5

RISCV_ISA_Spec_Tour

Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
HTML
35
star
6

RISCV_ISA_Formal_Spec_in_BSV

A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
Bluespec
20
star
7

Bluespec_BSV_Formal_Semantics

Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
Haskell
18
star
8

Book_BLang_RISCV

Book to (1) learn BLang (BSV) using a RISC-V example and (2) learn to design a pipelined RISC-V CPU using BSV for HDL coding
TeX
11
star
9

goParseBSV

A standalone parser for BSV (Bluespec SystemVerilog) written in Go
Go
10
star
10

RISC-V_Intro

TeX
9
star
11

Enigma_Cryptol_Bluespec_BSV

Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
Verilog
8
star
12

Tutorial_at_HPCA-29

An AWS-FPGA Testbed for Architecture Research on RISC-V CPUs, Accelerators, and Memory Systems
Verilog
8
star
13

Multithreaded_Architectures_1993

Slides from Multithreaded Architectures tutorial 1993 by Rishiyur S. Nikhil
4
star
14

Experimental_RISCV_Feature_Model

An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features
Python
2
star
15

Misc_Utilities

Miscellaneous Utilities
Python
1
star