mballance/amba_sys_ip

Stars
9
Rank 1,939,727 (Top 39 %)
Language SystemVerilog
License
Apache License 2.0
Created over 8 years ago
Updated almost 6 years ago

mballance/amba_sys_ip

mballance

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AMBA-protocol system IP

clusterv-soc

Quad cluster of RISC-V cores with peripherals and local memory

fwrisc-s

uvm-sc

UVM SystemC source, with my own additions

sveditor-ref-designs

Reference designs for use in SVEditor benchmarking

egtkwave

GTKWave embedded in Eclipse

sv_bfms

SystemVerilog BFMs with bindings for UVM, etc

socblox

Packaged open-source IP blocks and tools for easily assembling system-on-chip designs

caravel_fwpayload

Test project for the Open MPW shuttle

bmk

Bare-Metal Kernel framework for embedded environments

wb_sys_ip

Core IP for creating wishbone systems

ciostream

Cython wrapper around C++ iostream

psi

codbg

Hw/Sw co-debug tool combining GTKWave and GDB

uex

Portable Micro-Executor Framework

rocket_soc

Simple SoC based around the rocket-chip RISC-V generator

cocotb-sc

SystemC binding that supports running cocotb in a SystemC environment

simscripts

Basic simulation script and makefiles for executing simulation-based tests

fpgamgr

Management software for embedded processors connected to an FPGA fabric

oc_wb_ip

Wishbone-based IP blocks from opencores.org wrapped up with SystemVerilog interfaces

cudd

Mirror of CUDD 3.0.0, with the addition of CMake-based build

uvm_sdv

Software-Driven Verification extension library for UVM

coremesh

SoC composed of 2d mesh of cores with chip-to-chip connectivity

mballance.github.io

wb_dma

fwrisc-piton-soc

SoC involving fwrisc and and the openpiton interconnect

ucoro

Experimental micro co-routine implementation for embedded systems

fpio

FIFO Protocol I/O block

std_protocol_if

Provides SystemVerilog interface definitions for standard protocols, such as AXI4, Wishbone, etc

synthscripts

Synthesis scripts

PeakRDL-pss

PSS export generator for PeakRDL