Matthew Ballance (@mballance)
github

mballance

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  • Stars
    star
    91
  • Global Rank 222,433 (Top 8 %)
  • Followers 123
  • Following 47
  • Registered almost 13 years ago
  • Most used languages
    SystemVerilog     27.6 %
    C++
         20.7 %
    C
         17.2 %
    Verilog     13.8 %
    Assembly
         6.9 %
    Tcl     3.4 %
    Makefile     3.4 %
    Python
         3.4 %
    CSS
         3.4 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 47,638
  • Country Ranking
    SystemVerilog     50
    Verilog     164
    Assembly
         433
    Tcl     451
    Makefile     2,958
    C
         8,583
    C++
         8,678

Top repositories

1

clusterv-soc

Quad cluster of RISC-V cores with peripherals and local memory
Verilog
20
star
2

fwrisc-s

Assembly
9
star
3

amba_sys_ip

AMBA-protocol system IP
SystemVerilog
9
star
4

uvm-sc

UVM SystemC source, with my own additions
C++
6
star
5

sveditor-ref-designs

Reference designs for use in SVEditor benchmarking
Assembly
5
star
6

egtkwave

GTKWave embedded in Eclipse
C
4
star
7

sv_bfms

SystemVerilog BFMs with bindings for UVM, etc
SystemVerilog
4
star
8

socblox

Packaged open-source IP blocks and tools for easily assembling system-on-chip designs
SystemVerilog
3
star
9

caravel_fwpayload

Test project for the Open MPW shuttle
Verilog
2
star
10

bmk

Bare-Metal Kernel framework for embedded environments
C
2
star
11

wb_sys_ip

Core IP for creating wishbone systems
SystemVerilog
2
star
12

ciostream

Cython wrapper around C++ iostream
C++
2
star
13

psi

C++
2
star
14

codbg

Hw/Sw co-debug tool combining GTKWave and GDB
C++
2
star
15

uex

Portable Micro-Executor Framework
C
2
star
16

rocket_soc

Simple SoC based around the rocket-chip RISC-V generator
SystemVerilog
2
star
17

cocotb-sc

SystemC binding that supports running cocotb in a SystemC environment
2
star
18

simscripts

Basic simulation script and makefiles for executing simulation-based tests
Makefile
1
star
19

fpgamgr

Management software for embedded processors connected to an FPGA fabric
C++
1
star
20

oc_wb_ip

Wishbone-based IP blocks from opencores.org wrapped up with SystemVerilog interfaces
SystemVerilog
1
star
21

cudd

Mirror of CUDD 3.0.0, with the addition of CMake-based build
C
1
star
22

uvm_sdv

Software-Driven Verification extension library for UVM
C
1
star
23

coremesh

SoC composed of 2d mesh of cores with chip-to-chip connectivity
Verilog
1
star
24

mballance.github.io

Github Pages
CSS
1
star
25

wb_dma

Verilog
1
star
26

fwrisc-piton-soc

SoC involving fwrisc and and the openpiton interconnect
1
star
27

ucoro

Experimental micro co-routine implementation for embedded systems
C++
1
star
28

fpio

FIFO Protocol I/O block
SystemVerilog
1
star
29

std_protocol_if

Provides SystemVerilog interface definitions for standard protocols, such as AXI4, Wishbone, etc
SystemVerilog
1
star
30

synthscripts

Synthesis scripts
Tcl
1
star
31

PeakRDL-pss

PSS export generator for PeakRDL
Python
1
star