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MERN-eCommerce
eCommerce web app using Mongo DB. Express, React and NodeLinux-Cpp-Project-Setup
This repository consists of a comprehensive folder structure with the source-code/scripts for inter-process communication, Doxygen source-code documentation, Catch2 Unit Testing, Gcov/Lcov Code-Coverage Analysis and, multi-level Makefiles. This project is intended for setting up C/C++ projects on Linux.Page-Replacement-Algorithms
This project evaluates how applications respond to a variety of page replacement algorithms. A memory simulator is built to evaluate memory performance using traces from real or simulated applications. Code written for FIFO, LRU, LFU, MFU, and Optimal page replacement.Computer-System-Design
Finite State Machine on Anvyl Spartan-6 FPGA: The purpose of this project is to learn and practice synthesizable FSM construction to be tested on a FPGA board in Verilog. Design an FSM for use as a controller for a vending machine. The system has five (5) inputs: quarter, nickel, dime, soda, and diet. Further details in the project description.eCommerceBuilder
E-Commerce Builder WebsiteDSA_Implementations
Data structures and algorithms implementation in C++ for technical interviewTech-News-Reader
Android app that provides latest Hacker News tech articles (Java, SQLite, Web API)PseudoGen
Pseudocode Generator Android Appauthentication-firebase
React based auth using firebaserobofriends
First React JS app to add and search friends from a listmaharshi66
Readme file for Github ProfileFace-Recognition-Backend
Backend for the face recognition app using Node.js, Express.js and PostgreSQLFPGA-Design_1
VHDL project to build a count-down timer with preset time using the seven-segment display. Basys-3 FPGA board has been used to test and verify correctness. Further details in project description.React-Tic-Tac-Toe
React Based Tic Tac Toe GameOS_Project3
The purpose is to learn how to use semaphores to protect a limited size resource. A circular buffer with 15 positions (each position stores 1 character) is to be used to communicate information between two threads (producer and consumer).FPGA-Design_2
VHDL project for designing a simple digital lock to provide an approach for identity authentication. This lock operates in three modes: programming, normal and locked. Basys-3 FPGA board used to test and verify correctness of the FSM built for the digital lock. Further details in the project description.FPGA_MatOp
Implementing and testing matrix multiplication/addition algorithms on FPGA boards. – Input matrices are sent to FPGA from host terminal – Operations of FPGA are sent from host terminal • The above two need UART receiver – After the algorithm is finished, the results are displayed in a terminal on the host system through a UART transmitterDigital-Circuit-Synthesis
Provided with code of the clique partitioning algorithm implementation in C, develop several modules which can call the clique partitioning code to build the datapath synthesis tool. Read project description for further details.Face-Detection-Web-App
React based application with Front-end & Back-End with React, Node, Express, and PostgreSQLLove Open Source and this site? Check out how you can help us