Discover maharshi66/FPGA-Design_1 Open Source project

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Language VHDL
Created almost 6 years ago
Updated almost 6 years ago

maharshi66

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VHDL project to build a count-down timer with preset time using the seven-segment display. Basys-3 FPGA board has been used to test and verify correctness. Further details in project description.

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VHDL project for designing a simple digital lock to provide an approach for identity authentication. This lock operates in three modes: programming, normal and locked. Basys-3 FPGA board used to test and verify correctness of the FSM built for the digital lock. Further details in the project description.

VHDL

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Implementing and testing matrix multiplication/addition algorithms on FPGA boards. – Input matrices are sent to FPGA from host terminal – Operations of FPGA are sent from host terminal • The above two need UART receiver – After the algorithm is finished, the results are displayed in a terminal on the host system through a UART transmitter

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Provided with code of the clique partitioning algorithm implementation in C, develop several modules which can call the clique partitioning code to build the datapath synthesis tool. Read project description for further details.

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Face-Detection-Web-App

React based application with Front-end & Back-End with React, Node, Express, and PostgreSQL

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maharshi66/FPGA-Design_1

maharshi66

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