CDBUS IP Core

(This is an 8-bit version, please switch to the corresponding branch for the 32-bit version.)

1. CDBUS Protocol
2. Block Diagram
3. Registers
4. Interface
5. Examples
6. Simulation
7. Ready To Use Devices
8. License

CDBUS Protocol

CDBUS is a protocol for Asynchronous Serial Communication, it has a 3-byte header: [src_addr, dst_addr, data_len], then user data, and finally 2 bytes of CRC. (Same as MODBUS CRC.)

It's suitable for one-to-one communication, e.g. UART or RS-232. In this case, the address for each side are usually carefully selected and fixed, e.g: [0x55, 0xaa, data_len, ...], and the backward is: [0xaa, 0x55, data_len, ...]. (data_len ≤ 255.)

The CDBUS protocol is more valuable for bus communication, e.g. RS-485, M-LVDS or Single Line UART. In this case, it supports:

Arbitration Mode (CDBUS-A)

• It introduces an arbitration mechanism that automatically avoids conflicts like the CAN bus.
• Support dual baud rate, provide high speed communication, the baud rate in the data phase is up to: sys_freq ÷ 3. (e.g. 50 Mbps for 150 MHz sys_freq.)
• Supports unicast, multicast and broadcast.
• The maximum user data size is 253 bytes.
• Hardware packing, unpacking, verification and filtering, save your time and CPU usage.
• Backward compatible with traditional RS-485 hardware (The arbitration function still works).

The protocol timing example, include only one user data byte:
(You can set the length of time to enter idle and wait to send.)

Tips:

• When a high-priority node needs to send unimportant data, you can dynamically increase the send wait time (TX_PERMIT_LEN).

Arbitration example:

Break Sync Mode (CDBUS-BS)

In CDBUS-A mode, if the low-speed part takes a lot of time, it will be a communication efficiency bottleneck.

In this case, single-rate peer-to-peer bus communication can be implemented by CDBUS-BS mode:

• The TX_PERMIT_LEN parameter is configured differently for different nodes, and the difference needs to be large enough to avoid conflicts.
• If any node has pending tx frame before TX-permit point, then start send at the TX-permit point.
• Or wait until the idle time exceeds MAX_IDLE_LEN, then send a break character to bring the bus out of idle state.

The CDBUS-BS mode is suitable for high-speed applications with few nodes, and it is also suitable for software implementation.

Block Diagram

Operation

Registers

SETTING:

FILTERS:

Match from top to bottom:

It is recommended to reserve the address from 0xe0 to 0xfe as the multicast address.

The default value 0xff of FILTERn means not enabled.

DIV_xx_x:

Baud rate divider value: DIV_xx[15:0] = sys_freq ÷ baud_rate − 1

The minimum value is 2.

INT_FLAG:

Reading this register will automatically clear bit7, bit6, bit4, bit3 and bit2.

INT_MASK:

Output of irq = ((INT_FLAG & INT_MASK) != 0).

RX_CTRL:

TX_CTRL:

RX_PAGE_FLAG:

Value zero indicate the frame in current RX page is correct;
Non-zero indicate the pointer of last received byte of the disturbed frame, include CRC.

Interface

    parameter DIV_LS = 346,         // default: 115200 bps for 40MHz clk
    parameter DIV_HS = 346


    input           clk,            // core clock
    input           reset_n,        // asynch active low reset
    input           chip_select,    // reduce ram_rx power consumption
    output          irq,            // interrupt output

    // avalon-mm slave interface, read and write without latency
    // support burst read and write (normally for REG_TX and REG_RX)
    input   [4:0]   csr_address,
    input           csr_read,
    output  [7:0]   csr_readdata,
    input           csr_write,
    input   [7:0]   csr_writedata,

    // connect to external PHY chip, e.g. MAX3485
    input           rx,
    output          tx,
    output          tx_en

Examples

    # Configuration
    
    write(REG_SETTING, [0x11])                  # Enable push-pull output
    
    
    # TX
    
    write(REG_TX, [0x0c, 0x0d, 0x01, 0xcd])     # Write frame without CRC
    while (read(REG_INT_FLAG) & 0x20) == 0:     # Make sure we can successfully switch to the next page
        pass
    write(REG_TX_CTRL, [0x03])                  # Trigger send by switching TX page
    
    
    # RX
    
    while (read(REG_INT_FLAG) & 0x02) == 0:     # Wait for RX page ready
        pass
    header = read(REG_RX, len=3)
    data = read(REG_RX, len=header[2])
    write(REG_RX_CTRL, [0x03])                  # Finish read by switching RX page

Test

Install iverilog (>= v10) and cocotb, goto tests/ folder, run ./test_all.sh or ./test_all.sh test_xxx.py. (You can checkout the waveform cdbus.vcd by GTKWave.)

Ready To Use Devices

The CDCTL controller family uses the CDBUS IP Core, which provide SPI, I²C and PCIe peripheral interfaces.
E.g. The tiny CDCTL-Bx module support SPI and I²C interfaces:
(This module is completely open source, including the source code and gerber files, in the example/ directory.)

More relevant projects that may interest you:

• CDBUS GUI: https://github.com/dukelec/cdbus_gui
• CDNET: https://github.com/dukelec/cdnet

License

This Source Code Form is subject to the terms of the Mozilla
Public License, v. 2.0. If a copy of the MPL was not distributed
with this file, You can obtain one at https://mozilla.org/MPL/2.0/.
Notice: The scope granted to MPL excludes the ASIC industry.
The CDBUS protocol is royalty-free for everyone except chip manufacturers.

Copyright (c) 2017 DUKELEC, All rights reserved.