ben-marshall/latex-boilerplate

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Created almost 9 years ago
Updated over 8 years ago

ben-marshall/latex-boilerplate

ben-marshall

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A simple latex boilerplate with makefile for common commands.

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

verilog-parser

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

uart

A simple implementation of a UART modem in Verilog.

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

verilog-dot

A simple dot file / graph generator for Verilog syntax trees.

microcoder

Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.

verilog-doc

A basic documentation generator for Verilog, similar to Doxygen.

doxygen-themes

A collection of the various Doxygen Theme customisations I have created and used.

verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

tim

A small CPU core complete with compiler and ISA specification. Eventually....

vanilla-riscv

Vanilla RISC-V core, implementing RV32IMC

riscv-multi-cycle

WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*

aes-sboxes

Somewhere to put different implementations of the AES SBox

ann-playground

Code I develop while learning about Artificial Neural Networks