Discover ben-marshall/croyde-riscv Open Source project

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41
Rank 668,415 (Top 14 %)
Language SystemVerilog
License
MIT License
Created over 4 years ago
Updated almost 3 years ago

ben-marshall

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A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

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A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

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Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.

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verilog-doc

A basic documentation generator for Verilog, similar to Doxygen.

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A collection of the various Doxygen Theme customisations I have created and used.

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verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

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A small CPU core complete with compiler and ISA specification. Eventually....

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Vanilla RISC-V core, implementing RV32IMC

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WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*

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Somewhere to put different implementations of the AES SBox

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latex-boilerplate

A simple latex boilerplate with makefile for common commands.

TeX

ann-playground

Code I develop while learning about Artificial Neural Networks

Python

ben-marshall/croyde-riscv

ben-marshall

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