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14
Rank 1,438,076 (Top 29 %)
Language SystemVerilog
License
BSD 3-Clause "New...
Created over 2 years ago
Updated over 2 years ago

WajahatRiaz

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Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.

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RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

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Config files for my GitHub profile.

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WajahatRiaz/AHB-Lite-Protocol-Verification

WajahatRiaz

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