Domipheus/TPU

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135
Rank 269,297 (Top 6 %)
Language VHDL
Created over 9 years ago
Updated over 8 years ago

Domipheus/TPU

Domipheus

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TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

TPU

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

Some code in vhdl/top and vhdl/dvid is not owned by myself. Please refer to those files for information.

This is implemented with ISE Webpack (The free Xilinx tools) however the project is not committed here - yet.

This is the implementation being written about over at http://labs.domipheus.com/blog/category/projects/tpu/

RPU

Basic RISC-V CPU implementation in VHDL.

ArtyS7-RPU-SoC

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

TeensyZ80

Code and related parts of the TeensyZ80 project.

ArtyS7

Where Arty S7 projects are kept. MIT License unless file headers state otherwise.

UART

Simple UART implementation in VHDL

misc

General things not associated with a particular project.

miniSpartan3

Projects for the miniSpartan3 board from Scarab Hardware

SDDatalogger1

A 4-channel analog SD Card datalogger with RTC

BenchPower1

Schematics, Firmware & Simulations for a simple linear Bench Power Supply