Domipheus/ArtyS7-RPU-SoC

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Language VHDL
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Apache License 2.0
Created about 6 years ago
Updated about 4 years ago

Domipheus/ArtyS7-RPU-SoC

Domipheus

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Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

RPU

Basic RISC-V CPU implementation in VHDL.

TPU

TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

TeensyZ80

Code and related parts of the TeensyZ80 project.

ArtyS7

Where Arty S7 projects are kept. MIT License unless file headers state otherwise.

UART

Simple UART implementation in VHDL

misc

General things not associated with a particular project.

miniSpartan3

Projects for the miniSpartan3 board from Scarab Hardware

SDDatalogger1

A 4-channel analog SD Card datalogger with RTC

BenchPower1

Schematics, Firmware & Simulations for a simple linear Bench Power Supply