Discover @zslwyuan Open Source projects

Tingyuan LIANG (@zslwyuan)

zslwyuan

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526
Global Rank 53,310 (Top 2 %)
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Registered almost 8 years ago
Most used languages

C++
40.0 %

Python
24.0 %

VHDL 16.0 %

Ada
8.0 %

MATLAB
8.0 %

Verilog 4.0 %
Location 🇭🇰 Hong Kong
Country Total Rank 210
Country Ranking

Ada
1

VHDL 1

Verilog 2

MATLAB
20

C++
25

Python
529

LLVM-9.0-Learner-Tutorial

A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

AMF-Placer

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

Light-HLS

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

PAAS_V1.0

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

Multi-User-Transmit-Beamforming-Linear-Regression-Convex-Optimization-Tutorial

In this work, we use convex optimization package in MATLAB to implement multi-user transmit beamforming problem and linear regression. This is the homework 2 of ELEC 5470 Convex Optimization, HKUST.

Hi-DMM

Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

Zynq_HLS_DDR_Dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

LLVM-11-Tutorials

A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.

High-Performance-Karatsuba-Multiplier-HLS-FPGA

Implement High-Performance Karatsuba Multiplier in High-Level Synthesis (HLS) for FPGA Based on Recursive Template

KMeans-Emails-Clustering-Visualization-NLP

KMeans-Emails-Clustering-Visualization-NLP: KMeans is used to cluster the emails. The words in the contents of emails are tokenlized and stemmed. This project transforms the corpus into vector space using tf-idf.By multidimensional scaling, the clustering result is visualized.

AutoCellLibX

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining

Barrier-Method-LASSO

This project, based on MATLAB, is an implementation of barrier method to solve LASSO problem. The barrier method is designed with centering step based on newton method.

Zedboard_Intergrating_HLS_IP_AND_DDR

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

google-ngrams-2020updated

Python scripts updated in 2020 for retrieving CSV data from the Google Ngram Viewer and plotting it in XKCD style. The Python script for retrieving ngram data was originally modified from the script at www.culturomics.org.

Zedboard-xfOpenCV-Optical-Flow

xfOpenCV Optical Flow implemented on Zedboard with built aarch32 OpenCV libraries

Staublis_Computer_Vision_Course_Project

It is a course project finished during ELEC 5640 Robot Manipulation. The mission of the project has been described in the report. The coding is .... quite rough but it may help other to deal with staublis and CV. The report is very detailed and hope it helps. Please be careful of the robot arm and don't hurt yourself and others.

Zynq_HLS_DDR_AXI_IPs_Multiple_Clock

TCP-IPv6-OpenCV-Video-Streaming

Implement OpenCV video streaming based on TCP/IPv6

LLVM-9-for-Light-HLS

LLVM-9 with arbitrary precision integer patch for Light-HLS

Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

gem5-HDL_v1.0

Tensorflow_Customized_Optimizer_Tutorial

A previous project based on tensorflow in COMP 5212, HKUST. The project includes user-customized momentum SGD optimizer, CNN and CAE (convolutional autoencoder).

Sklearn_Tutorial

A previous project based on scikit-learn in COMP 5212, HKUST. The project includes logistic regression model, multi-layer perceptron, SVM and related cross-validation procedures.

Odecomp

Odecomp: Online Tensor Decomposition for the Model Compression of Neural Network

Summary-Notes-for-Machine-Learning-COMP5212

Summary Notes for Machine Learning (COMP5212), which might help to review what have learned from the course

Parallel-Computing-Tutorials-OMP-MPI-CUDA

These are the implementations of the previous assignments from the course COMP 5212 Parallel Computing. Various solutions have been tried and current source codes are based on those get the highest performance on the server. These source codes cover the range from OpenMP, MPI to CUDA. The assignments are required to solve the shortest path problem and Bellman-ford algorithm has been involved, considering that there could be negative circles in the graph. Thanks to Prof. LUO's detailed lectures and TAs' patient guide.