IEEE-754-Floating-point-multiplication-using-Weighted-2-stage-Booth-algorithm

This is a project to design and implement a IEEE 754 Floating-point standard multiplication using Weighted 2_stage Booth algorithm to improve its performance in comparison with traditional method (array multiplication). More information of this project can be found on PowerPoint file.

SingleCycleRV32I

This is a project to design and implement a single cycle RV32I CPU to execute basic instructions of RISC-V ISA such as R, I, U, S, B type. This project is still being developed.