Discover mfkiwl/SpinalHDL-FPGA-IPbox Open Source project by @mfkiwl

KiCAD PCB files for KiwiSDR project including active antenna and bias tee

112

KiwiSDR_PCB

KiCad Layout

InvariantEKF_GNSS_IMU

Forked from Beagle_SDR_GPS for specialized add-on SDR board with 16-Bit ADC which improved from KiwiSDR.

FlyDog_SDR_GPS

Multi-GNSS Precise Point Postioning with Ambiguity Resolution

PPP_AR

OFDM-Joint-Radar-Communications

Digital Image Correlation. OpenCV with Python wrapper

DIC

integrated navigation using INS/GNSS

IntegratedNavigation

parallella-platform

GPS software-defined receiver (SDR) which acquires and tracks a single GPS L1 C/A signal.

GNSS-Software-Defined-Radio

E203_dma

Left/Right Invariant Extended Kalman Filter Localization for KITTI Dataset.

RIEKF-KITTI

Utilities for SAR and InSAR processing

insar

MCU programmer using CMSIS-DAP (DAPLink), using Keil MDK's *.FLM Flashing Algorithm

MCUProgFast

一个SLAM算法方向学生的痛苦之旅，包括leetcode刷题、c++面经和SLAM相关知识点。欢迎协作！

slam_and_leetcode

zjv-core

10 stage RISC-V (riscv) core capable of booting RV64 Linux and Debian on FPGA

Scala

Livox_Fisheye_Fusion

Continuing programming of GNSS algorithm and application

GNSS_Programming

esp32-ice40up5k

Files for a dev board containing an ESP32-Wrover module and an ice40up5k-sg48 FPGA

Codes to calculate solar-sensor zenith and azimuth angles directly from hyperspectral images collected by UAV. Works only for UAVs that have high resolution GNSS/IMU unit.

uav-solar-sensor-angle

Applied to the modified livox_ros_driver pointcloid2 format

FAST_LIO_Modified

Navigation_GNSS

Crusoe Exposed: Transmeta TM5xxx Architecture - text from an anonymous reverse engeneerer

TransmetaCrusoeExposed

vins_mono application 计算机视觉life

vins_mono_noted

A multi robot collaborative dense SLAM

coxgraph

A template EasyEDA project with Raspberry Pi RP2040, USB-UART Bridge, 16MB Flash and 800mA LDO optimised for JLCPCB PCBA. 🔌 🔨

rp2040-base-pcb-template

GNSS-spoofing

A spoofing demonstration using GNSS and GNSS-SDR-SIM

SHA256_Hardware_Accelerator

SHA256 Hardware Accelerator Synthesizable Verilog RTL

Open Source HDLC and fault tolerant frame syncronization IPs using VHDL

ad936x_lvds_if

ad936x lvds interface

fyp-rca-taiga

GNSS_INS

UBX_Decode_ESF-NAV

Freelance_SDR_FPGA_2019-FaultTolerant

This module is a Verilog Implementation of a fully pipelined Arithmetic Logic Unit which is capable of performing all sorts of computations on Integers. The ARM 7 instruction set architecture is followed in the implementation which includes all of the standard operations with a control on weather to write the data back to register file, or not. It also takes care of the dependencies by using data forwarding methods.

Pipelined-ALU

Usefule link about MCU/FPGA/CPU/RTL design

useful-link-for-me

hlsVHDL_fixed_point_math

Installers for SIFT3D on various platforms.

SIFT3D-installers

Ace21064

RISCV Superscalar Microprocessor Implemention

fpga-cnn-accelerator

First translation of C program for vector addition into RTL VHDL

FPGA-Vector-Addition-RTL-VHDL

Verilog 93 implementation of a special multiplexer for use in phased arrays

EmLab_Amp_HW-lpc4370

Hardware for 80dB amp

HTML

phased-array-Mux-FPGA

This repository contains MATLAB code used to complete HW3 for Fundamentals of GPS.

gps-hw3

verilog-advanced-synthesis-cookbook

Verilog 12-channel intensity correlator for FPGAs

interferometer

ROS-NAVIGATION-WITH-IMU-SENSOR-AND-MAGNETOMETER

STM32MP1_TestBoard

HTML

hgdb-rtl

This repository contains the implementation of a single cycle based on RISC-V ISA and implemented on `LOGISIM`

RV32I-Single-Cycle

gnss_compass

2个UBX M8T实现双天线侧向功能

hlsVHDL_memory_library

Implementation of a 32-bit ULA using VHDL.

ula32bits

multi_layer_perceptron_verilog

RISC-V RV32IM compatible CPU created from scratch. Includes MMU and D/I-Caches

ArmleoCPU

CassieHardware

Rectify Difference in Vertical Direction in Binocular Cameras based on Fearture Points Matching. As a consequence, the Cloud Points and Depth Map would be calculated.

Stereo-Matching

A repository for launching GNSS/IMU Tightly-coupled localization method aided with fisheye camera on ROS

gnss_imu

RF(register file) and ALU

Verilog-Register-File-and-ALU

this repository gives an overview and step by step description on how to make an 8 bit processor using verilog HDL on an FPGA.

rk-open-docs

internal docs

Shell

8_bit_processor

Developing sensor using Computer Vision to monitor movement and produce vibration trace of critical bridge elements.

Video_Analytics

GNSS_SDR-2

This is the new and improved Plex Automatic Pre-roll script with a GUI

rtk_gps_src

Plex-Automatic-Pre-roll-GUI

Self Driving Car project using MATLAB and RWTH Mindstorms NXT Toolbox for LEGO® Mindstorms NXT

M.A.Nt.I.S

VHDL Model of a Cell Processor Synergistic Processing Unit

SPU_Multimedia_Processor

J-LINK Commander like tool for JLink, adding HardFault diagnosis and SVD-based peripheral register access.

JLKCmdr

CAMERA-IF for Raspberry Pi Pico (RP2040)

piocamera

RISC-V_Vector_Accelerator_For_ML

hlsVHDL_ethernet

USV board for HAMNET Nodes

HamPWR-lpc4370

SDRAM-Controller-1

Verilog 拥有极简用户接口的 SDR SDRAM 控制器

SIFT-1

SIFT Verilog

hlsVHDL_fpga_interconnect

matlabINS

radar_slam

hlsVHDL_dynamic_simulation_library

generic non-negative least squares solver

nnls_solver

Verilog-Program-Counter-and-Shifter

PC(Program counter) and SHIFTER(arithmatic and logical)

High precision mapping using LIDAR, GNSS and IMU

lidar-mapping

GNSS or DCF77 disciplined OCXO based on hardware by DL4ZAO and DL7UKM.

GPSDO_by_DF4IAH

Detect-Interference-on-GNSS-Signals

Apply LSTM to Detect Interference in Satellite Signals

aim is straight forward -> the power analysis of each RISC-V instructions , such that in future an extremely superior RISC-V ISA core can be designed , that can give best performance in both prospective -> highest speed during execution of any task and along with lowest power consumption as well !

Benchmark-of-RISC-V-INSTRUCTIONS-concerning-power-consumption-

Makefile

Monocular_ORB_SLAM2_System

Development branch: Multicore RV32IMA w/ MMU, Cache capable of booting Linux. two stage: RISC-V RV32IM compatible CPU created from scratch. Includes MMU and D/I-Caches

ArmleoCPU-1

Multiplying a square matrix on hardware using one clock cycle and a 3-stage pipeline.

Matrix-Multiplication-VHDL

A low power, 6 stage in order pipeline, 2 privilege level (M and U), clock cicle of 100MHz, 32 bit RISC-V softcore for FPGA. Written in SystemVerilog.

RV32IMF-MicroGT_01

The concept of the WRAN software uses the IEEE 802.22 frame structure for prototyping to make use of super frames and preambles for cognitive channel management, which allows a dynamic resource allocation between base stations, but also between multiple users at one base station. Orthogonal Frequency Division Multiple Access (OFDMA) is used in the upper layers, as Modulation techniques QPSK, 16-QAM and 64-QAM is supported. The software will support a connection-oriented MAC layer with cognitive functionality for dynamic and adaptive scheduling and management of coexistence of base stations in the same time-frequency domain (super frames).

RPX-100-SDR

simultaneous localization and mapping (SLAM) - To build a map of the environment and to simultaneously localize within this map for mobile robots navigating in unknown environments in absence of external referencing systems

Graph-SLAM

This implementation is on Xilinx Artix-7 100T FPGA with Vivado using Verilog and hosts the RISC-V processor. It introduces a hardware synthesized inverse kinematics algorithm that controls 6 degrees of freedom robotic arms and a sensor-based automatic control system. All systems are hardware-synthesized and work simultaneously. (2022-06-25~ (If I have some free time, I'll start working on it.))

fpga-6dof-inverse-kinematics

gnss_multipath_mitigator

Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit can perform addition, subtraction, multiplication, division and fused multiply-add/subtract operations. Bfloat16 is a 16-bit floating-point data type developed at Google and currently used in their Tensor Processing Units (TPU's). Thanks to its dynamic range, the Bfloat16 format can be useful for Machine Learning applications that work well with low-precision representations of data. This Bfloat16 unit will be used to add custom RISC-V floating-point instructions to a RISC-V processor that can potentially be used as a hardware accelerator for Machine Learning applications. This model will also be tested on and FPGA and possibly modified to achieve optimal performance. Work is still in progress.

Bfloat16-Floating-Point-Arithmetic-Unit