• Stars
    star
    1
  • Language
  • Created about 2 years ago
  • Updated about 2 years ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Проект предоставляет функционал по построению графиков различной степени сложности с использованием c++ и opencv

More Repositories

1

I2C-FPGA-Verilog-HDL

In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.
Verilog
11
star
2

SPI-FPGA-Verilog-HDL

In this project, I am developing a verilog SPI interface for FPGA
Verilog
2
star
3

PWM-FPGA-VERILOG

I am developing a PWM parametric module.
Verilog
1
star
4

image-tracing-in-camera

image forming by a non-ideal lens with a round pupil
MATLAB
1
star
5

RISE_EDGE_PULSE_LENGTH_CONVERTER

Here I am developing a pulse length converter
Verilog
1
star
6

Pulse-shortening-device-FPGA-VERILOG-HDL

In this project, I am developing a signal shortener (single-osc).
Verilog
1
star
7

Debounce-FPGA-Verilog-HDL

In this project, I develop bounce suppression systems for attaching electro-mechanical elements to an FPGA
Verilog
1
star
8

geometric-shape-classification

В данном проекте реализуется решение задачи классификации геометрических фигур в условиях сложной фоно-целевой обстановки
MATLAB
1
star
9

custom-histogram-equalization

Реализуется алгоритм эквализации гистограммы изображения с получением квазиравномерного распределения частот интенсивностей с настраиваемой точностью
1
star
10

UART-FPGA-Verilog-HDL

In this project, I am developing an interface for the FPGA platform that implements the UART protocol. Hardware description language selected by Verilog
Verilog
1
star